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Concurrent Conditional and Selected Signal Assignment in VHDL

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This article will review the concurrent signal assignment statements in VHDL.

This article will first review the concept of concurrency in hardware description languages. Then, it will discuss two concurrent signal assignment statements in VHDL: the selected signal assignment and the conditional signal assignment. After giving some examples, we will briefly compare these two types of signal assignment statements.

Please see my article introducing the concept of VHDL if you're not familiar with it.

Concurrent vs. Sequential Statements

To understand the difference between the concurrent statements and the sequential ones, let’s consider a simple combinational circuit as shown in Figure 1.

Figure 1. A combinational circuit.

If we consider the operation of the three logic gates of this figure, we observe that each gate processes its current input(s) in an independent manner from other gates. These physical components are operating simultaneously. The moment they are powered, they will “concurrently” fulfill their functionality. Note that while, in practice, the AND gate has a delay to produce a valid output, this does not mean that the OR gate will stop its functionality and wait until the output of the AND gate is produced. The OR gate will function all the time; however, its output will not be valid until its inputs have settled.

Now, let’s examine the VHDL description of Figure 1. This is shown below:

The main part that we are here interested in is the definition of the three gates:

Each of these lines describes a physical component in Figure 1. For example, the second line, which describes the OR gate, takes sig1 and c as inputs and produces the OR of these two values. We saw that the physical components of Figure 1 operate concurrently. Hence, it is reasonable to expect that the VHDL description of these gates should be evaluated in a concurrent manner. In other words, the above three lines of the code are executed at the same time and there is no significance to the order of these statements. As a result, we can rewrite the architecture section of the above code as below:

Since these statements are evaluated at the same time, we call them concurrent statements. This type of code is quite different from what we have learned in basic computer programming where the lines of code are executed one after the other. For example, consider the following MATLAB code:

This code produces out1=1 and out2=1 . However, if we change the order of the statements to the following, the program will stop working because we are trying to use sig1 before it is generated.

While the VHDL code describing Figure 1 was executed concurrently, the above MATLAB code is evaluated sequentially (i.e., one line after the other). VHDL supports both the concurrent statements and the sequential ones. It's clear that the concurrent VHDL statements will allow us to easily describe a circuit such as the one in Figure 1 above. In a future article, we'll see that the sequential VHDL statements allow us to have a safer description of sequential circuits. Furthermore, using the sequential VHDL, we can easily describe a digital circuit in a behavioral manner. This capability can significantly facilitate digital hardware design.

The following figure illustrates the difference between concurrent and sequential statements.

Figure 2. The difference between concurrent and sequential statements. Image courtesy of VHDL Made Easy .

Now let's take a look at two concurrent signal assignment statements in VHDL: “the selected signal assignment statement” and “the conditional signal assignment statement”.

Selected Signal Assignment or the “With/Select” Statement

Consider an n -to-one multiplexer as shown in Figure 3. This block should choose one out of its n inputs and transfer the value of this input to the output terminal, i.e., output_signal .

Figure 3. A multiplexer selects one of its n inputs based on the value of the control_expression.

The selected signal assignment allows us to implement the functionality of a multiplexer. For example, the VHDL code describing the multiplexer of Figure 3 will be

Here, the value of the control_expression will be compared with the n possible options, i.e., option_1 , option_2 , …, option_n . When a match is found, the value corresponding to that particular option will be assigned to the output signal, i.e., output_signal . For example, if control_expression is the same as option_2 , then value_2 will be assigned to the output_signal .

Note that the options of a “with/select” assignment must be mutually exclusive, i.e., one option cannot be used more than once. Moreover, all the possible values of the control_expression must be included in the set of the options. The following example clarifies these points.

Example 1 : Use the "with/select" statement to describe a one-bit 4-to-1 multiplexer. Assume that the inputs to be selected are a , b , c , and d . And, a two-bit signal, sel , is used to choose the desired input and assign it to out1 .

The code for this multiplexer is given below:

Note that since the std_logic data type can take values other than “0” and “1” , the last line of the “with/select” statement needs to use the keyword “ others ” to take all the possible values of sel into account.

The following figure shows the simulation of this code using the Xilinx ISE simulator. (In case you’re not familiar with ISE, see this tutorial .) As shown in this figure, from 0 nanosecond (ns) until 300 ns the select input, sel , is 00, and, hence, out1 follows the input a . Similarly, you can verify the intended operation for the rest of the simulation interval.

Figure 4. The ISE simulation for the multiplexer of Example 1.

Example 2 : Use the “with/select” statement to describe a 4-to-2 priority encoder with the truth table shown below.

The following VHDL code can be used to describe the above truth table:

The ISE simulation is shown in Figure 5.

Figure 5. The ISE simulation for the priority encoder of Example 2.

Conditional signal assignment or the “when/else” statement.

The “when/else” statement is another way to describe the concurrent signal assignments similar to those in Examples 1 and 2. Since the syntax of this type of signal assignment is quite descriptive, let’s first see the VHDL code of a one-bit 4-to-1 multiplexer using the “when/else” statement and then discuss some details.

Example 3 : Use the when/else statement to describe a one-bit 4-to-1 multiplexer. Assume that the inputs to be selected are a , b , c , and d . And, a two-bit signal, sel , is used to choose the desired input and assign it to out1 .

The code will be

In this case, the expressions after “when” are evaluated successively until a true expression is found. The assignment corresponding to this true expression will be performed. If none of these expressions are true, the last assignment will be executed. In general, the syntax of the “when/else” statement will be:

We should emphasize that the expressions after the “when” clauses are evaluated successively. As a result, the expressions evaluated earlier has a higher priority compared to the next ones. Considering this, we can obtain the conceptual diagram of this assignment as shown in Figure 6. This figure illustrates a conditional signal assignment with three “when” clauses.

Figure 6. The conceptual implementation of a “when/else” statement with three “when” clauses.

Let’s review the main features of the selected signal assignment and the conditional signal assignment.

“With/Select” vs. “When/Else” Assignment

As mentioned above, the options of a “with/select” assignment must be mutually exclusive, i.e., one option cannot be used more than once. Moreover, all the possible values of the control_expression must be included in the set of options. While the “with/select” assignment has a common controlling expression, a “when/else” assignment can operate on expressions with different arguments. For example, consider the following lines of code:

In this case, the expressions are evaluating two different signals, i.e., reset1 and clk .

For the “when/else” assignment, we may or may not include all the possible values of the expressions to be evaluated. For example, the multiplexer of Example 3 covers all the possible values of sel ; however, the above code does not. The above code implies that out1 should retain its previous value when none of the expressions are true. This causes the inference of a latch in the synthesized circuit.

Another important difference between the “with/select” and “when/else” assignment can be seen by comparing the conceptual implementation of these two statements. The priority network of Figure 6 involves a cascade of several logic gates. However, the “with/select” assignment avoids this chain structure and has a balanced structure. As a result, in theory, the “with/select” statement may have better performance in terms of the delay and area (see RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability , Xilinx HDL Coding Hints , and Guide to HDL Coding Styles for Synthesis ).

In practice, we generally don’t see this difference because many synthesis software packages, such as the Xilinx XST, try not to infer a priority encoded logic. Though we can use the PRIORITY_EXTRACT constraint of XST to force priority encoder inference, Xilinx strongly suggests that we use this constraint on a signal-by-signal basis; otherwise, the constraint may guide us towards sub-optimal results. For more details see page 79 of the XST user guide .

• Concurrent statements are executed at the same time and there is no significance to the order of these statements. This type of code is quite different from what we have learned in basic computer programming where the lines of code are executed one after the other.
• The selected signal assignment or the "with/select" assignment allows us to implement the functionality of a multiplexer.
• The options of a “with/select” assignment must be mutually exclusive, i.e., one option cannot be used more than once. Moreover, all the possible values of the control_expression must be included in the set of the options.
• For the "when/else" statement, the expressions after the “when” clauses are evaluated successively. As a result, the expressions evaluated earlier has a higher priority compared to the next ones.
• One important difference between the “with/select” and “when/else” assignment can be seen by comparing the conceptual implementation of these two statements. The "when/else" statement has a priority network; however, the “with/select” assignment avoids this chain structure and has a balanced structure.

To see a complete list of my articles, please visit  this page .

  Featured image used courtesy of Parallella .

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Great content. The link to the ISE guide requires password. Can we get that posted again? Thanks!

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Signal Assignments in VHDL: with/select, when/else and case

Sometimes, there is more than one way to do something in VHDL. OK, most of the time , you can do things in many ways in VHDL. Let’s look at the situation where you want to assign different values to a signal, based on the value of another signal.

With / Select

The most specific way to do this is with as selected signal assignment. Based on several possible values of a , you assign a value to b . No redundancy in the code here. The official name for this VHDL with/select assignment is the selected signal assignment .

When / Else Assignment

The construct of a conditional signal assignment is a little more general. For each option, you have to give a condition. This means that you could write any boolean expression as a condition, which give you more freedom than equality checking. While this construct would give you more freedom, there is a bit more redundancy too. We had to write the equality check ( a = ) on every line. If you use a signal with a long name, this will make your code bulkier. Also, the separator that’s used in the selected signal assignment was a comma. In the conditional signal assignment, you need the else keyword. More code for the same functionality. Official name for this VHDL when/else assignment is the conditional signal assignment

Combinational Process with Case Statement

The most generally usable construct is a process. Inside this process, you can write a case statement, or a cascade of if statements. There is even more redundancy here. You the skeleton code for a process (begin, end) and the sensitivity list. That’s not a big effort, but while I was drafting this, I had put b in the sensitivity list instead of a . Easy to make a small misstake. You also need to specify what happens in the other cases. Of course, you could do the same thing with a bunch of IF-statements, either consecutive or nested, but a case statement looks so much nicer.

While this last code snippet is the largest and perhaps most error-prone, it is probably also the most common. It uses two familiar and often-used constructs: the process and the case statements.

Hard to remember

The problem with the selected and conditional signal assignments is that there is no logic in their syntax. The meaning is almost identical, but the syntax is just different enough to throw you off. I know many engineers who permanenty have a copy of the Doulos Golden Reference Guide to VHDL lying on their desks. Which is good for Doulos, because their name gets mentioned all the time. But most people just memorize one way of getting the job done and stick with it.

• VHDL Pragmas (blog post)
• Records in VHDL: Initialization and Constraining unconstrained fields (blog post)
• Finite State Machine (FSM) encoding in VHDL: binary, one-hot, and others (blog post)
• "Use" and "Library" in VHDL (blog post)
• The scope of VHDL use clauses and VHDL library clauses (blog post)

VHDL Logical Operators and Signal Assignments for Combinational Logic

In this post, we discuss the VHDL logical operators, when-else statements , with-select statements and instantiation . These basic techniques allow us to model simple digital circuits.

In a previous post in this series, we looked at the way we use the VHDL entity, architecture and library keywords. These are important concepts which provide structure to our code and allow us to define the inputs and outputs of a component.

However, we can't do anything more than define inputs and outputs using this technique. In order to model digital circuits in VHDL, we need to take a closer look at the syntax of the language.

There are two main classes of digital circuit we can model in VHDL – combinational and sequential .

Combinational logic is the simplest of the two, consisting primarily of basic logic gates , such as ANDs, ORs and NOTs. When the circuit input changes, the output changes almost immediately (there is a small delay as signals propagate through the circuit).

Sequential circuits use a clock and require storage elements such as flip flops . As a result, changes in the output are synchronised to the circuit clock and are not immediate. We talk more specifically about modelling combinational logic in this post, whilst sequential logic is discussed in the next post.

Combinational Logic

The simplest elements to model in VHDL are the basic logic gates – AND, OR, NOR, NAND, NOT and XOR.

Each of these type of gates has a corresponding operator which implements their functionality. Collectively, these are known as logical operators in VHDL.

To demonstrate this concept, let us consider a simple two input AND gate such as that shown below.

The VHDL code shown below uses one of the logical operators to implement this basic circuit.

Although this code is simple, there are a couple of important concepts to consider. The first of these is the VHDL assignment operator (<=) which must be used for all signals. This is roughly equivalent to the = operator in most other programming languages.

In addition to signals, we can also define variables which we use inside of processes. In this case, we would have to use a different assignment operator (:=).

It is not important to understand variables in any detail to model combinational logic but we talk about them in the post on the VHDL process block .

The type of signal used is another important consideration. We talked about the most basic and common VHDL data types in a previous post.

As they represent some quantity or number, types such as real, time or integer are known as scalar types. We can't use the VHDL logical operators with these types and we most commonly use them with std_logic or std_logic_vectors.

Despite these considerations, this code example demonstrates how simple it is to model basic logic gates.

We can change the functionality of this circuit by replacing the AND operator with one of the other VHDL logical operators.

As an example, the VHDL code below models a three input XOR gate.

The NOT operator is slightly different to the other VHDL logical operators as it only has one input. The code snippet below shows the basic syntax for a NOT gate.

• Mixing VHDL Logical Operators

Combinational logic circuits almost always feature more than one type of gate. As a result of this, VHDL allows us to mix logical operators in order to create models of more complex circuits.

To demonstrate this concept, let’s consider a circuit featuring an AND gate and an OR gate. The circuit diagram below shows this circuit.

The code below shows the implementation of this circuit using VHDL.

This code should be easy to understand as it makes use of the logical operators we have already talked about. However, it is important to use brackets when modelling circuits with multiple logic gates, as shown in the above example. Not only does this ensure that the design works as intended, it also makes the intention of the code easier to understand.

• Reduction Functions

We can also use the logical operators on vector types in order to reduce them to a single bit. This is a useful feature as we can determine when all the bits in a vector are either 1 or 0.

We commonly do this for counters where we may want to know when the count reaches its maximum or minimum value.

The logical reduction functions were only introduced in VHDL-2008. Therefore, we can not use the logical operators to reduce vector types to a single bit when working with earlier standards.

The code snippet below shows the most common use cases for the VHDL reduction functions.

Mulitplexors in VHDL

In addition to logic gates, we often use multiplexors (mux for short) in combinational digital circuits. In VHDL, there are two different concurrent statements which we can use to model a mux.

The VHDL with select statement, also commonly referred to as selected signal assignment, is one of these constructs.

The other method we can use to concurrently model a mux is the VHDL when else statement.

In addition to this, we can also use a case statement to model a mux in VHDL . However, we talk about this in more detail in a later post as this method also requires us to have an understanding of the VHDL process block .

Let's look at the VHDL concurrent statements we can use to model a mux in more detail.

VHDL With Select Statement

When we use the with select statement in a VHDL design, we can assign different values to a signal based on the value of some other signal in our design.

The with select statement is probably the most intuitive way of modelling a mux in VHDL.

The code snippet below shows the basic syntax for the with select statement in VHDL.

When we use the VHDL with select statement, the <mux_out> field is assigned data based on the value of the <address> field.

When the <address> field is equal to <address1> then the <mux_out> signal is assigned to <a>, for example.

We use the the others clause at the end of the statement to capture instance when the address is a value other than those explicitly listed.

We can exclude the others clause if we explicitly list all of the possible input combinations.

• With Select Mux Example

Let’s consider a simple four to one multiplexer to give a practical example of the with select statement. The output Q is set to one of the four inputs (A,B, C or D) depending on the value of the addr input signal.

The circuit diagram below shows this circuit.

This circuit is simple to implement using the VHDL with select statement, as shown in the code snippet below.

VHDL When Else Statements

We use the when statement in VHDL to assign different values to a signal based on boolean expressions .

In this case, we actually write a different expression for each of the values which could be assigned to a signal. When one of these conditions evaluates as true, the signal is assigned the value associated with this condition.

The code snippet below shows the basic syntax for the VHDL when else statement.

When we use the when else statement in VHDL, the boolean expression is written after the when keyword. If this condition evaluates as true, then the <mux_out> field is assigned to the value stated before the relevant when keyword.

For example, if the <address> field in the above example is equal to <address1> then the value of <a> is assigned to <mux_out>.

When this condition evaluates as false, the next condition in the sequence is evaluated.

We use the else keyword to separate the different conditions and assignments in our code.

The final else statement captures the instances when the address is a value other than those explicitly listed. We only use this if we haven't explicitly listed all possible combinations of the <address> field.

• When Else Mux Example

Let’s consider the simple four to one multiplexer again in order to give a practical example of the when else statement in VHDL. The output Q is set to one of the four inputs (A,B, C or D) based on the value of the addr signal. This is exactly the same as the previous example we used for the with select statement.

The VHDL code shown below implements this circuit using the when else statement.

• Comparison of Mux Modelling Techniques in VHDL

When we write VHDL code, the with select and when else statements perform the same function. In addition, we will get the same synthesis results from both statements in almost all cases.

In a purely technical sense, there is no major advantage to using one over the other. The choice of which one to use is often a purely stylistic choice.

When we use the with select statement, we can only use a single signal to determine which data will get assigned.

This is in contrast to the when else statements which can also include logical descriptors.

This means we can often write more succinct VHDL code by using the when else statement. This is especially true when we need to use a logic circuit to drive the address bits.

Let's consider the circuit shown below as an example.

To model this using a using a with select statement in VHDL, we would need to write code which specifically models the AND gate.

We must then include the output of this code in the with select statement which models the multiplexer.

The code snippet below shows this implementation.

Although this code would function as needed, using a when else statement would give us more succinct code. Whilst this will have no impact on the way the device works, it is good practice to write clear code. This help to make the design more maintainable for anyone who has to modify it in the future.

The VHDL code snippet below shows the same circuit implemented with a when else statement.

Instantiating Components in VHDL

Up until this point, we have shown how we can use the VHDL language to describe the behavior of circuits.

However, we can also connect a number of previously defined VHDL entity architecture pairs in order to build a more complex circuit.

This is similar to connecting electronic components in a physical circuit.

There are two methods we can use for this in VHDL – component instantiation and direct entity instantiation .

• VHDL Component Instantiation

When using component instantiation in VHDL, we must define a component before it is used.

We can either do this before the main code, in the same way we would declare a signal, or in a separate package.

VHDL packages are similar to headers or libraries in other programming languages and we discuss these in a later post.

When writing VHDL, we declare a component using the syntax shown below. The component name and the ports must match the names in the original entity.

After declaring our component, we can instantiate it within an architecture using the syntax shown below. The <instance_name> must be unique for every instantiation within an architecture.

In VHDL, we use a port map to connect the ports of our component to signals in our architecture.

The signals which we use in our VHDL port map, such as <signal_name1> in the example above, must be declared before they can be used.

As VHDL is a strongly typed language, the signals we use in the port map must also match the type of the port they connect to.

When we write VHDL code, we may also wish to leave some ports unconnected.

For example, we may have a component which models the behaviour of a JK flip flop . However, we only need to use the inverted output in our design meaning. Therefore, we do not want to connect the non-inverted output to a signal in our architecture.

We can use the open keyword to indicate that we don't make a connection to one of the ports.

However, we can only use the open VHDL keyword for outputs.

If we attempt to leave inputs to our components open, our VHDL compiler will raise an error.

• VHDL Direct Entity Instantiation

The second instantiation technique is known as direct entity instantiation.

Using this method we can directly connect the entity in a new design without declaring a component first.

The code snippet below shows how we use direct entity instantiation in VHDL.

As with the component instantiation technique, <instance_name> must be unique for each instantiation in an architecture.

There are two extra requirements for this type of instantiation. We must explicitly state the name of both the library and the architecture which we want to use. This is shown in the example above by the <library_name> and <architecture_name> labels.

Once the component is instantiated within a VHDL architecture, we use a port map to connect signals to the ports. We use the VHDL port map in the same way for both direct entity and component instantiation.

Which types can not be used with the VHDL logical operators?

Scalar types such as integer and real.

Write the code for a 4 input NAND gate

We can use two different types of statement to model multiplexors in VHDL, what are they?

The with select statement and the when else statement

Write the code for an 8 input multiplexor using both types of statement

Write the code to instantiate a two input AND component using both direct entity and component instantiation. Assume that the AND gate is compiled in the work library and the architecture is named rtl.

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courses:system_design:vhdl_language_and_syntax:process_execution

• Process Execution

Fundamentals

An architecture can contain processes and concurrent statements which are all active in parallel. The connection of the parallel parts is established via signals and sensitivity lists. Concurrent statements can be interpreted as functionally equivalent processes with a sensitivity list containing all those values that are going to be read in this process. If, for example, the process P1 was triggered, e.g. by a clock edge, its statements are executed one after another. This way it is possible to execute parts of the code only after an active edge has occurred.

Let us assume that a couple of signals were modified. The changes will not take effect until the process execution has finished. According to the schematic, these updated values will trigger C1 and P1 which will trigger P1 and C2 in turn, and so on.

The execution of the statements continues until a stable state is reached, i.e. no events are generated any more.

Concurrent versus Sequential Execution

If the same two signal assignments appear in the VHDL code, once as concurrent statement in the architecture and once in a process, the result will differ substantially:

• In the first case, two parallel signal assignments are actually made to the signal. This is only allowed for resolved types, for which a so called resolution functions is present to decide which value is actually driven.
• In the second case, the first assignment is executed and its result is stored. Afterwards, this result is overwritten by another assignment, so that only the last signal assignment is carried out.

Signal Update

• Future value used within the simulator core, only
• Past value ≠ current value: event
• Signal values are updated at the end of a process execution: the old current value of a signal is overwritten by the future value
• Several process calls at one single moment of the simulation are possible

The signal update mechanism is essential for a VHDL simulator. Signals possess a past, a current and a future value within the simulators signal management functions. Signal assignments in a process always assign the value to the future value of the signal.

The future value is copied to the current value in the signal update phase after the process execution is finished i.e. the process is suspended.

Several process calls at one signal moment of the simulation are possible?

Several process calls at one single moment of the simulation are possible!

Delta Cycles (1)

• One moment of simulation
• One loop cycle = “delta cycle”
• Delta time is orthogonal to simulation time
• Signals are updated
• Signal assignments are stored
• To execute further processes

A simulation cycle always consists of a signal update and a process execution phase. Several of these so called delta cycles may have to be carried out in order to achieve a stable state of the system. The number of delta cycles has no effect on the time in the simulated time frame! It just affects the time that is necessary to carry out the simulation. The delta cycles are lined up orthogonally to the simulation time.

Delta Cycles (2)

• Several delta cycles at any moment of the simulation

At the beginning, all signals are updated and a list of all processes that are triggered by the signal changes is created. All the processes of this list are executed one after another in delta cycle 1. When the execution is finished, the signal updates will be carried out and a new process list will be created. This continues until the process list remains empty, that means no further processes are triggered by the signal events. Now, statements which induce a real time step (’wait for …’, ’… after …’) are carried out and the simulation time advances for the specified amount of time.

Delta Cycles - Example

• Y receives the current value of A (no change)
• X receives the current value of B ( new value)
• Z receives the current value of X (no change)
• signal update
• X receives the current value of B (no change)
• Z receives the current value of X (new value)
• No future events on A, B, X

Let us assume that the value of signal B changes. In the example, the process is triggered by this event on B and is activated for the first time. The future value of X is given the current value of B. At the end of the process, the future value of X is transferred to its current value.

This change of value on X results in an event that calls the process for the second time. Now, the current value of X is written to the future value of Z (B and X remain the same). During the signal update phase only Z’s value changes which is not listed in the sensitivity list, i.e. the process will not be called again. The signals X and Z are set to the value from B this way. This example is for demonstrative purposes, only. The intermediate signal X conceals the functionality of the process and would not be used in practice. Generally, variables, which are not subject to the update mechanism, should be used instead.

Process Behavior

• The process is an endless loop
• It is stopped by a wait-statement
• The sensitivity list is equivalent to a wait-statement
• A process with a sensitivity list must not contain any wait statement

Basically, a process has to be considered as an endless loop.

The continuous process execution can be interrupted via wait statements. The use of a sensitivity list is equivalent to a WAIT ON-statement. If a sensitivity list is present, WAIT statements must not appear in the process.

Postponed Process

• Processes which are executed in the last delta cycle of a certain moment
• Wait statements of the time 0
• Signal assignments without delay (for 0 ns)

Postponed processes are always carried out in the last delta cycle.

This means that this process can access already stable signals at this point of simulation time.

In postponed processes, WAIT statements with 0 ns and signal assignments without delay are not permitted.

Please note that postponed processes can only be used in simulation, not in synthesis.

• ...is the minimum timestep in a simulation.
• ...updates exactly one signal.
• neither of them
• ...is executed concurrently together with other processes and concurrent statements
• ...can be controlled by wait statement or sensitivity list

Chapters of System Design > VHDL Language and Syntax

• General Issues
• VHDL Structural Elements
• Extended Data Types
• Sequential Statements
• Subprograms
• Subprogram Declaration and Overloading
• Concurrent Statements

Chapter 4 - Behavioral Descriptions

Section 3 - signals and processes.

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Using Multiple Processes In VHDL

• Thread starter jerryt
• Start date Nov 18, 2011
• Nov 18, 2011

Junior Member level 3

I have another easy question: If I use the same signal in multiple processes in a behavioral architecture using VHDL how do I know which process will run first? Is it top-down meaning the first process run into in code and then the next process in code, etc? For example (from top down of how the code is written): process (clk,A) [sequential statements] end process; process (clk, A, reset,) [sequential statements] end process; Which process will run first? Do I have to worry about the dependencies of signal A since it is in two different processes? Also, can I use port signals and declared signals in the sensitivity list for a process? Thanks!  

Advanced Member level 3

It is an event based system. The key is the "nonblocking" assignments. in this case, you have clk'event. this flags both processes for evaluation. nonblocking assignments within each process are evaluated, but the results are not assigned to the signals at this time. After all processes for clk'event have been evaluated, all assignments are made. Each assignment triggers a 'event for that signal -- any combinatorial process is now updated. for this reason, a sequential process will typically only need clk and reset. otherwise A'event will cause the process to be evaluated needlessly -- neither the reset nor clock edge cases will be true, so no actual code will be reached on that evaluation. Shared variables use blocking assignments. as such they are only used in very few use-cases in VHDL.  

TrickyDicky

Advanced member level 7.

signals work on a scheduling system. They do no get updated until the process they are updated in suspends or waits. I am a bit worried you ask about multiple processes, because a signal can only be updated in a single process. You cannot assign a signal in multiple processes or it counts as a multple driver error (or in the case of a std_logic, you will get 'X'). Anyway, back to the scheduling thing, because of this, you can write code like this: Code: process(clk) begin if rising_edge(clk) then a <= 1; a <= 2; a <= 3; end if; end process; Because the signal takes the last assignment, another process can read "a" at the next clock edge (or delta) and would read 3, because the 1 and 2 assignments got overwritten by the 3rd one. On to your questions: Which process will run first? Neither. They both run at the same time. Do I have to worry about the dependencies of signal A since it is in two different processes? No, because you can only update it in a single process. can I use port signals and declared signals in the sensitivity list for a process? Yes. But with a clocked process, you only need clock in a sensitivity list (which is probably a port) and reset if you want async reset. A port is a signal. Permute mentions shared variables that do allow writes from multiple processes, and when they get updated will depend on the behaviour of your simulator (or carefully constructed code). I would not recommend using them though. A synthesisor will treat them as a signal during compillation (and you'll get the same multiple driver errors)  

Thanks to everyone for their responses. TrickyDicky: You say "You cannot assign a signal in multiple processes or it counts as a multple driver error (or in the case of a std_logic, you will get 'X'). " Just to be clear for sure, do you mean that I cannot use the same signal in multiple processes sensitivity lists. For example if I had: process (A,B,C, clk) .... end process; process (B, reset) .... Are you saying that I could not use "B" in more than one process because I would get an error when trying to synthesize? Thanks!  

Administrator

If this was a problem then you wouldn't be able to use the clock in more than one processes... There in no problem to read but you can only write a value from one process. You may be interested in https://www.edaboard.com/threads/195444/ it is a way to set/clear a flag from different processes or clock domains Alex  

Thanks Alexan. So what you are saying is that in the code below I could not write to B in both processes and it would cause an error. I can only write to B in only "1 process". Is that correct? process (A,B,C, clk) B <= tempB end process; process (B, reset) B <= A xor C end process; ------------------------------------  

Yes, this can't be done because you are using hardware description language, it represents a real circuit so you can't control one electrical signal output from two different drivers. Alex  

Alexan told you the hardware answer, but in VHDL the code you posted is illegal (ie. you'll get a syntax error) unless B is a resolved type (like std_logic). This allows drivers from multiple processes, but with std_logic doing this will almost always result in B being 'X' (unknown) when you simulate, and when you try to compile it you'll just get a multiple driver error. The only time from a hardware perspective you can drive 1 signal from multiple places is via tri-state buffers (and their RTL descriptions)  

Both great answers - I appreciate it. Tricky - What if I use a signal assignment that is not part of the port assignment of the entity? For example, in the code below I use a signal assignment "temp C" outside of the port assignment. In the first process I set tempC = B. In the second process I use tempC as my sensitive signal to begin running the 2nd process. Is this legal in VHDL code? Thanks! entity example port (A, B, C, clk : in std_logic Z : out std_logic); end example; begin architecture behav of example signal tempA, tempB, tempC process (A,B,C, clk) begin tempB <= A tempC <= B end process; process (tempC) B <= A xor C end process;  

Yes you can use that, write the signal in one process and trigger another process with an event on that signal. Alex  

Alex: However, we cannot write to a port signal in one process and trigger another process with an event on this port signal. Is that correct? I appreciate your help, thanks!  

I'm not sure about that but I think if the port is a buffer or inout so that you are able to read the value then it could trigger another process. I have never used anything similar. Alex Edit . it obviously can't be a buffer since you are asking for an output so ignore the buffer part Edit 2 : I have no idea why I said that buffer is not an output, it is an output that can be read. I have seen some recommendations to avoid it, it can be replaced with a signal that drives the output, when you want to read the output value you just read the signal. VHDL coding tips and tricks: How to stop using "buffer" ports in VHDL?  

• Nov 19, 2012

Newbie level 1

I have a similar problem. a vending machine controller takes coins and changes states with clk. however when the coin stuck at the machine, it should not be regarded as infinite coins so i need to prevent state change in that case. Here is my code : Code: Process(rst,clk) Begin if(rst='1') Then present_state <= st0; elsif( rising_edge(clk) ) then present_state <= next_state; end if; end process; Process(present_state,coin5_in,coin10_in,coin25_in) Begin if Case present_state IS When st0 => coke_out <= '0'; coin5_out <= '0'; coin10_out <= '0'; cstate <= "0000"; if(coin5_in) then next_state <= st5; elsif(coin10_in) then next_state <= st10; elsif(coin25_in) then next_state <= st25; else next_state <= st0; end if; if i used coin_valid signal(boolean) for both process, it is the same error  

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Assign signal in many processes

I try to learn VHDL language I don't understand a strange thing. This thing refers to the signals from an architecture.

My question is: Why we can't assign bit signal, integer signal, etc in more than one process/ concurrent assign. But I saw, we can assign in more than one process Std_logic_vector signal and Std_logic signal.

• "But I saw, we can assign in more than one process Std_logic_vector signal and Std_logic signal." Please show us the code where you think that is correctly used. –  Oldfart Commented Jan 19, 2019 at 16:46
• Welcome to Stack Overflow. Please read through the Help Center > Asking section, and ensure your question follows the guidelines, since that will give you most success getting answers in this forum. –  Morten Zilmer Commented Jan 19, 2019 at 16:50
• "It is an error if, after the elaboration of a description, a signal has multiple sources and it is not a resolved signal.", IEEE Std 1076-2008 6.4.2.3 Signal declarations. "The resolution function associated with a resolved signal determines the resolved value of the signal as a function of the collection of inputs from its multiple sources.", 4.6 Resolution functions. The resolution function for std_logic or std_logic_vector (named resolved) is found in the std_logic_1164 package body. Restrictions on multiple drivers can be target device limited and defined by synthesis tools. –  user1155120 Commented Jan 19, 2019 at 18:39

It is an error if, after the elaboration of a description, a signal has multiple sources and it is not a resolved signal.

IEEE Std 1076-2008 6.4.2.3 Signal declarations.

The resolution function associated with a resolved signal determines the resolved value of the signal as a function of the collection of inputs from its multiple sources.

4.6 Resolution functions.

The resolution function for std_logic or std_logic_vector (named resolved) is found in the std_logic_1164 package body.

Restrictions on multiple drivers can be target device limited and defined by synthesis tools.

made @user1155120 's comment a community wiki answer

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Why do we assign our outputs to signals first in VHDL?

I saw in many VHDL codes that data/control outputs are first assigned to signals and then to output ports, and not instantly to the output ports.

I'll give an example:

My question is, why do we not assign some_data instantly to the data_out port? Why does it "have to go through" the signal data_out_sig ? Does this have anything to do with synthesis? Is it common practice?

4 Answers 4

I will tell you a scenario. Suppose you are creating an entity with

2 input ports : A,B 2 output ports : C,D

Suppose the output C is generated from A and B using some logic. And Suppose D is found to be directly related with C. For example:

D = compliment of C

So it is compelling to write in the code: D = not C directly, instead of using a logic expression with and A and B. However VHDL semantics don't allow you to read the output port C and hence you cannot implement such an expression. So what you can do is turn that port into a buffer port. Some people also make use in/out port for this purpose. But that makes thing complex. So a simple solution is to use some local internal signal C_int, and "use" it like the output port inside your code. So that you can implement the logic for C into this internal signal, read it and manipulate with it. Finally assigning this internal signal to the output port, outside all the process blocks, completes the requirement. An example illustration of what is happening inside the circuit:

It's because you couldn't read from ports of type OUT in VHDL.

If the value driving an OUT port was to be read within the design, a signal had to used to hold it, then that signal assigned to the OUT port.

The capability to do so was added in VHDL-2008. However, a huge amount of designs were created before 2008 and before take-up of VHDL-2008 became available in software tools. These designs would therefore use the signal-drives-OUT method.

As an aside, it depends upon your circumstances as an engineer but the option to use VHDL-2008 may well not be available to you. Some companies will require design revisions to be synthesised or simulated by a specific version of software (Quartus, Xilinx ISE, ModelSim etc.) with no changes to the design project settings, so you cannot use VHDL-2008. I have worked in a great many companies that do this, defence companies for example. Moving to a newer version of software introduces an unnecessary risk of unexpected changes that can discredit all the testing and experience gained with that firmware so far, with the time and expense that go with that. So there is a lot of value in writing 'middle of the road' VHDL that will be accepted by the widest range of software tools that you can, rather than using syntax specific to VHDL-2008 or VHDL-2002. The downsides of this are few or none - I'm not aware of anything that you can't do in the earlier versions that vast majority of designs require. As I said, it depends upon your circumstances and is something to consider. For me, I would definitely use signal-drives-OUT. Being completely portable between software tools and versions is valuable to me and one of my priorities.

If the signal from an output port also is read back you have to use the 'buffer' port type.

That by itself would not be a problem but if that 'output' port goes up a hierarchical chain of modules you have to change the output of each model to 'buffer'.

To avoid the hassle it is easiest to use a local variable and in one place assign that to the output.

I prefer to use that technique only for output ports that are also read back but I can image somebody preferring to use it all the time.

• 1 \$\begingroup\$ You can read back from OUT ports in VHDL-2008. So, this is either obsolete practice or a concession to obsolete tools. \$\endgroup\$ –  user16324 Commented Dec 29, 2017 at 19:25

Notice that data_out is defined as an output. That means it can only be written to. However, you cannot read from it.

So you can directly go

data_out <= some_data;

That works fine. But suppose some_data needed to be continuously modified.

For my purposes of these examples, I will assume the data types are integers and not std_logic like in your original post.

I cannot do

data_out <= data_out + 1

because this would require a read prior to adding the one. Since you cannot read from data_out, this would not work.

data_out <= some_data + 1

and this would work, but in doing so, I can no longer manipulate the result in the future because it is now stored in data_out and can no longer be read from.

If I want to manipulate the result in the future, then I have to go

data_out_sig <= some_data + 1; --can continue to reading and modify the result in the future data_out <= data_out_sig;

So you can assign data instantly to the output if you don't need to ever manipulate what is stored in data_out. For example, a conditional branch could decide that the output needs to be a '1' or '0'. You could write this directly to the output without an intermediary.

data_out <= 1;

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