Verilog Blocking & Non-Blocking

Blocking assignment statements are assigned using = and are executed one after the other in a procedural block. However, this will not prevent execution of statments that run in a parallel block.

Note that there are two initial blocks which are executed in parallel when simulation starts. Statements are executed sequentially in each block and both blocks finish at time 0ns. To be more specific, variable a gets assigned first, followed by the display statement which is then followed by all other statements. This is visible in the output where variable b and c are 8'hxx in the first display statement. This is because variable b and c assignments have not been executed yet when the first $display is called.

In the next example, we'll add a few delays into the same set of statements to see how it behaves.

Non-blocking

Non-blocking assignment allows assignments to be scheduled without blocking the execution of following statements and is specified by a symbol. It's interesting to note that the same symbol is used as a relational operator in expressions, and as an assignment operator in the context of a non-blocking assignment. If we take the first example from above, replace all = symobls with a non-blocking assignment operator , we'll see some difference in the output.

See that all the $display statements printed 'h'x . The reason for this behavior lies in the way non-blocking assignments are executed. The RHS of every non-blocking statement of a particular time-step is captured, and moves onto the next statement. The captured RHS value is assigned to the LHS variable only at the end of the time-step.

So, if we break down the execution flow of the above example we'll get something like what's shown below.

Next, let's use the second example and replace all blocking statements into non-blocking.

Once again we can see that the output is different than what we got before.

If we break down the execution flow we'll get something like what's shown below.

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Blocking and Non-blocking Assignment in Verilog

  • Assignment is only done in procedural block(always ot initial block)
  • Both combintational and sequential circuit can be described.
  • Assignment can only possible to reg type irrespect of circuit type

Let's say we want to describe a 4-bit shift register in Verilog. For this, we are required to declare a 3-bit reg type variable.

The output of shift[0] is the input of shift[1], output of shift[1] is input of shift[2], and all have the same clock. Let's complete the description using both assignment operator.

Non-Blocking Assignment

When we do synthesis, it consider non-blocking assignment separately for generating a netlist. If we see register assignment in below Verilog code, all register are different if we consider non-blocking assignment separately. If you do the synthesis, it will generate 3 registers with three input/output interconnects with a positive edge clock interconnect for all register. Based on the Verilog description, all are connected sequentially because shift[0] is assigned d, shift[1] is assigned shift[0], and shift[2] is assigned shift[1].

Blocking Assignment

If we use blocking assignment and do the syhtheis, the synthesis tool first generate netlist for first blocking assignment and then go for the next blocking assignment. If in next blocking assignment, if previous output of the register is assigned to next, it will generate only a wire of previously assigned register.

In below Verilog code, even though all looks three different assignment but synthesis tool generate netlist for first blocking assigment which is one register, working on positive edge of clock, input d and output shift[0]. Since blocking assignment is used, for next blocking assignment, only wire is generated which is connected to shift[0]. Same is for next statement a wire is generated which is connected to shift[0].

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Blocking vs. Nonblocking in Verilog

The concept of Blocking vs. Nonblocking signal assignments is a unique one to hardware description languages. The main reason to use either Blocking or Nonblocking assignments is to generate either combinational or sequential logic. In software, all assignments work one at a time. So for example in the C code below:

The second line is only allowed to be executed once the first line is complete. Although you probably didn’t know it, this is an example of a blocking assignment. One assignment blocks the next from executing until it is done. In a hardware description language such as Verilog there is logic that can execute concurrently or at the same time as opposed to one-line-at-a-time and there needs to be a way to tell which logic is which.

<=     Nonblocking Assignment

=      Blocking Assignment

The always block in the Verilog code above uses the Nonblocking Assignment, which means that it will take 3 clock cycles for the value 1 to propagate from r_Test_1 to r_Test_3. Now consider this code:

See the difference? In the always block above, the Blocking Assignment is used. In this example, the value 1 will immediately propagate to r_Test_3 . The Blocking assignment immediately takes the value in the right-hand-side and assigns it to the left hand side. Here’s a good rule of thumb for Verilog:

In Verilog, if you want to create sequential logic use a clocked always block with Nonblocking assignments. If you want to create combinational logic use an always block with Blocking assignments. Try not to mix the two in the same always block.

Nonblocking and Blocking Assignments can be mixed in the same always block. However you must be careful when doing this! It’s actually up to the synthesis tools to determine whether a blocking assignment within a clocked always block will infer a Flip-Flop or not. If it is possible that the signal will be read before being assigned, the tools will infer sequential logic. If not, then the tools will generate combinational logic. For this reason it’s best just to separate your combinational and sequential code as much as possible.

One last point: you should also understand the semantics of Verilog. When talking about Blocking and Nonblocking Assignments we are referring to Assignments that are exclusively used in Procedures (always, initial, task, function). You are only allowed to assign the reg data type in procedures. This is different from a Continuous Assignment . Continuous Assignments are everything that’s not a Procedure, and only allow for updating the wire data type.

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  • Getting started with verilog
  • Hello World
  • Procedural Blocks
  • Non-blocking assignments
  • Simple counter
  • Synthesis vs Simulation mismatch

verilog Procedural Blocks Non-blocking assignments

A non-blocking assignment ( <= ) is used for assignment inside edge-sensitive always blocks. Within a block, the new values are not visible until the entire block has been processed. For example:

Notice the use of non-blocking ( <= ) assignments here. Since the first assignment doesn't actually take effect until after the procedural block, the second assignment does what is intended and actually swaps the two variables -- unlike in a blocking assignment ( = ) or assignments in other languages; f1 still has its original value on the right-hand-side of the second assignment in the block.

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Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog

There are Two types of Procedural Assignments in Verilog.

  • Blocking Assignments
  • Nonblocking Assignments

To learn more about Delay: Read  Delay in Assignment (#) in Verilog

Blocking assignments

  • Blocking assignments (=) are done sequentially in the order the statements are written.
  • A second assignment is not started until the preceding one is complete. i.e, it blocks all the further execution before it itself gets executed.

Blocking

Non-Blocking assignments

  • Nonblocking assignments (<=), which follow each other in the code, are started in parallel.
  • The right hand side of nonblocking assignments is evaluated starting from the completion of the last blocking assignment or if none, the start of the procedure.
  • The transfer to the left hand side is made according to the delays. An intra- assignment delay in a non-blocking statement will not delay the start of any subsequent statement blocking or non-blocking. However normal delays are cumulative and will delay the output.
  • Non-blocking schedules the value to be assigned to the variables but the assignment does not take place immediately. First the rest of the block is executed and the assignment is last operation that happens for that instant of time.

Non_Blocking

To learn more about Blocking and Non_Blocking Assignments: Read Synthesis and Functioning of Blocking and Non-Blocking Assignments

The following example shows  interactions  between blocking  and non-blocking for simulation only (not for synthesis).

Mixed

For Synthesis (Points to Remember):

  • One must not mix “<=” or “=” in the same procedure.
  • “<=” best mimics what physical flip-flops do; use it for “always @ (posedge clk..) type procedures.
  • “=” best corresponds to what c/c++ code would do; use it for combinational procedures.

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Non Blocking Proceduaral assignments

The non-blocking assignment statement starts its execution by evaluating the RHS operand at the beginning of a time slot and schedules its update to the LHS operand at the end of a time slot. Other Verilog statements can be executed between the evaluation of the RHS operand and the update of the LHS operand. As it does not block other Verilog statement assignments, it is called a non-blocking assignment.

A less than or equal to ‘<=’ is used as a symbol for the non-blocking assignment operator.

  • If <= symbol is used in an expression then it is interpreted as a relational operator. 
  • If <= symbol is used in an assignment then it is interpreted as a non blocking operator. 

How race around condition is resolved in a nonblocking assignment?

If a variable is used in LHS of blocking assignment in one procedural block and the same variable is used in RHS of another blocking assignment in another procedural block.

In this example, 

Since procedural blocks (both initial and always) can be executed in any order.

In a non-blocking assignment statement no matter what is the order of execution, both RHS of the assignments (y <= data and data <= y) are evaluated at the beginning of the timeslot and LHS operands are updated at the end of a time slot. Thus, race around condition is avoided as there is no dependency on execution order and the order of execution of these two statements can be said to happen parallelly.

Verilog procedural assignment guidelines

For a beginner in Verilog, blocking and non-blocking assignments may create confusion. If are used blindly, it may create race conditions or incorrect synthesizable design. Hence, it is important to understand how to use them. To achieve synthesized RTL correctly, Verilog coding guidelines for blocking and non-blocking assignments are mentioned below

  • Use non-blocking assignments for modeling flip flops, latches, and sequential logic.
  • Use blocking assignment to implement combinational logic in always block.
  • Use non-blocking assignment to implement sequential logic in always block.
  • Do not mix blocking and non-blocking assignments in single always block i.e. For the implementation of sequential and combination logic in a single ‘always’ block, use non-blocking assignments.
  • Do not assign value to the same variable in the different procedural blocks.
  • Use non-blocking assignments while modeling both combination and sequential logic within the same always block.
  • Avoid using #0 delay in the assignments.

Verilog Tutorials

Verification Guide

SystemVerilog NonBlocking assignment

Nonblocking assignment.

  • non-blocking assignment statements execute in parallel
  • In the non-blocking assignment, all the assignments will occur at the same time. (during the end of simulation timestamp)

Nonblocking assignment example

In the below example, a and b are initialized with values 10 and 15 respectively, after that b is being assigned to a (a value will become 15), and value 20 is assigned to b. After assignment values expected in a and b are 15 and 20 respectively. but these values will get assigned only after the simulation time-stamp.

Simulator Output:

verilog non blocking assignment

Nonblocking assignment example-2

In the below example, a and b are initialized with value 10 and 15 respectively. x<=a+b and y<=a+b+x value of x is sum of a (10) and b (15). -> x=10+15=25. value of y is sum of a (10) ,b(15) and x (0) -> became at current simulation time-stamp value of x=0. new value will get assigned at the end of current time stamp, and new value will be available only after the current time-stamp). therefore y=10+15+0=25;

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COMMENTS

  1. Verilog Blocking & Non-Blocking

    Non-blocking assignment allows assignments to be scheduled without blocking the execution of following statements and is specified by a <= symbol. It's interesting to note that the same symbol is used as a relational operator in expressions, and as an assignment operator in the context of a non-blocking assignment.

  2. PDF I. Blocking vs. Nonblocking Assignments

    • Verilog supports two types of assignments within blocks, with subtly different behaviors. always Blocking assignment: evaluation and assignment are immediate always @ (a or b or c) begin x = a | b; y = a ^ b ^ c; z = b & ~c; 1. Evaluate a | b, assign result to 2. Evaluate a^b^c, assign result to 3. Evaluate b&(~c), assign result to x y z end

  3. Difference between blocking and nonblocking assignment Verilog

    Non-blocking assignment executes in parallel because it describes assignments that all occur at the same time. The result of a statement on the 2nd line will not depend on the results of the statement on the 1st line. Instead, the 2nd line will execute as if the 1st line had not happened yet. Share Cite Follow answered Nov 24, 2013 at 4:21

  4. Blocking and Non-blocking Assignment in Verilog

    Blocking and Non-blocking Assignment in Verilog When working with behavioural modeling in Verilog, there are two types of assigment which is known as blocking and non blocking assigment and both of them there is a operator, '=' operator for blocking assignment and '<=' operator for non blocking assigment.

  5. Blocking and Nonblocking Assignments in Verilog

    Blocking and Nonblocking Assignments in Verilog Blocking vs. Nonblocking in Verilog The concept of Blocking vs. Nonblocking signal assignments is a unique one to hardware description languages. The main reason to use either Blocking or Nonblocking assignments is to generate either combinational or sequential logic.

  6. How to interpret blocking vs non blocking assignments in Verilog

    How to interpret blocking vs non blocking assignments in Verilog? Ask Question Asked 13 years, 1 month ago Modified 9 years, 2 months ago Viewed 41k times 28 I am a little confused about how blocking and non blocking assignments are interpreted when it comes to drawing a hardware diagram.

  7. verilog Tutorial => Non-blocking assignments

    A non-blocking assignment ( <=) is used for assignment inside edge-sensitive always blocks. Within a block, the new values are not visible until the entire block has been processed. For example:

  8. PDF Advanced Verilog

    Advanced Verilog EECS 270 v10/23/06 Continuous Assignments review Continuously assigns right side of expression to left side. Limited to basic Boolean and ? operators. For example a 2:1 mux: ? operator assign D = (A= =1) ? B : C; // if A then D = B else D = C; Boolean operators assign D = (B & A) | (C & ~A); // if A then D = B else D = C;

  9. PDF Understanding Verilog Blocking and Nonblocking Assignments

    Understanding Verilog Blocking and Non-blocking Assignments International Cadence User Group Conference September 11, 1996 presented by Stuart Sutherland Sutherland HDL Consulting About the Presenter Stuart Sutherland has over 8 years of experience using Verilog with a variety of software tools.

  10. PDF Blocking and Non-blocking Assignments in Explicit and Implicit Style

    Verilog provides two kinds of behavioral assignment: the blocking assignment (=), which is similar to software as-signment statements found in most conventional pro-gramming languages, and the non-blocking assignment (<=), which is the more natural assignment statement to describe many hardware systems, especially for syn-thesis.

  11. Blocking And Nonblocking In Verilog

    Nonblocking Statements: Nonblocking statements allow you to schedule assignments without blocking the procedural flow. You can use the nonblocking procedural statement whenever you want to make several register assignments within the same time step without regard to order or dependence upon each other.

  12. PDF Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!

    This paper details how Verilog blocking and nonblocking assignments are scheduled, gives important coding guidelines to infer correct synthesizable logic and details coding styles to avoid Verilog simulation race conditions. 1.0 Introduction Two well known Verilog coding guidelines for modeling logic are:

  13. Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog

    There are Two types of Procedural Assignments in Verilog. Blocking Assignments Nonblocking Assignments To learn more about Delay: Read Delay in Assignment (#) in Verilog Blocking assignments Blocking assignments (=) are done sequentially in the order the statements are written.

  14. Non Blocking Procedural assignments

    As it does not block other Verilog statement assignments, it is called a non-blocking assignment. A less than or equal to '<=' is used as a symbol for the non-blocking assignment operator. Note If <= symbol is used in an expression then it is interpreted as a relational operator.

  15. Code Crafting: The Art of Blocking and Non-Blocking Assignments in Verilog

    Procedural Statements in Verilog, such as blocking and non-blocking assignments, are categorized as elements of procedural blocks, such as 'always' and 'initial.'

  16. SystemVerilog NonBlocking assignment

    Nonblocking assignment example. In the below example, a and b are initialized with values 10 and 15 respectively, after that b is being assigned to a (a value will become 15), and value 20 is assigned to b. After assignment values expected in a and b are 15 and 20 respectively. but these values will get assigned only after the simulation time ...

  17. Verilog Blocking and Non-blocking

    Verilog supports blocking and non-blocking assignments statements within the always block with their different behaviors. The blocking assignment is similar to software assignment statements found in most popular programming languages. The non-blocking assignment is the more natural assignment statement to describe many hardware systems ...

  18. Why we need non-blocking assignments in Verilog?

    Using non-blocking assignments: always@(posedge) a <= b; c <= d; So the two pieces of code above carry out the same process (parallel assignment of b to a and d to c, ignoring the race condition in case of blocking assignment).

  19. Help: Difference between Blocking and Non-blocking assignment

    Go to Verilog r/Verilog. r/Verilog ... ADMIN MOD Help: Difference between Blocking and Non-blocking assignment. I've been trying to understand the difference between blocking and non-blocking assignment for some time, but I haven't been able to wrap my head around it. Can someone explain it with a simple use case?

  20. <= Assignment Operator in Verilog

    "<=" is a non-blocking assignment operator in verilog."=" is a blocking assignment operator. Consider the following code.. always@(clk) begin a=b; end always@(clk) begin b=a; end The values of a and b are being exchanged using two different always blocks.. Using "=" here caused a race-around condition. ie. both the variables a and b are being ...

  21. verilog

    But I've been told that in Verilog, this might be dangerous -- specifically because non-blocking assignments can lead to inefficient or incorrect hardware structures, especially when used for initialization. I've also been told that non-blocking assignments may be interpreted differently between synthesis and simulation tools.