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Implementation of Machine Learning in VLSI Integrated Circuit Design

• Original Research
• Published: 04 January 2023
• Volume 4 , article number  137 , ( 2023 )

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• S. Shreyanth   ORCID: orcid.org/0000-0002-9991-5491 1 , 4 ,
• D. S. Harshitha   ORCID: orcid.org/0000-0003-4041-4243 2 &
• S. Niveditha   ORCID: orcid.org/0000-0003-3377-7345 3  

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Machine learning has made an impact on the area attributed to microchip, and it is initially used in automation. These techniques will eventually supplant the current VLSI design concept. Design creation has been automated by substituting time-consuming traditional concepts developed by experts. This development could result in a tremendous change in the realm of hardware computation and AI’s powerful analysis tools. As a result, during the last four decades, several tasks have been computerized, and a plethora of sophisticated tasks have been mechanized. And then if someone has invented a new concept (in terms of computing, analyzing, optimization, and inter-relationship manufacturing) and the invention process is computerized, major firms like IBM and Intel have their own CAD division to handle these issues for design automation. Several firms, including major electronic design automation company, sell CAD software’s based on the employment of intelligent tools at circuit development. ML had broadened the present reach by assisting with plausible solutions for an extensive kind on the subject problems as well as challenges in a different range of technical domains. Importance of machine learning in the EDA solutions industry has increased its capabilities by lowering the man-hours spent on design confirmation and its implementation, cost reductions, and design product productivity. In this article we have discussed the importance of the application of machine learning in VLSI chip design and development and how we implemented ML-oriented BIST.

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A Preliminary Taxonomy for Machine Learning in VLSI CAD

Machine Learning Perspective in VLSI Computer-Aided Design at Different Abstraction Levels

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Department of Electronics and Communication Engineering, Anna University, Chennai, Tamil Nadu, 600025, India

S. Shreyanth

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D. S. Harshitha

Department of Biotechnology, Rajalakshmi Engineering College, Chennai, Tamil Nadu, 602105, India

S. Niveditha

Data Science and Engineering, Birla Institute of Technology and Science, Pilani, Rajasthan, 333031, India

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Shreyanth, S., Harshitha, D.S. & Niveditha, S. Implementation of Machine Learning in VLSI Integrated Circuit Design. SN COMPUT. SCI. 4 , 137 (2023). https://doi.org/10.1007/s42979-022-01580-5

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Latest Research topics in vlsi design

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If we narrow down our discussion to research in areas like electronics, electrical, computer science, artificial intelligence , wireless communication and related fields, which are the base of everything in this high-tech world. In these fields researchers have developed applications (aided with technology) for every field ranging from biomedical to aerospace and construction, which were nowhere related to electronics or even current.

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Embedded Radiation sensor with OBIST structure for applications in mixed signal systems

Oscillation based testing (OBT) has proven to be a simple and effective test strategy for numerous kind of circuits. In this work, OBT is applied to a radiation sensor to be used as a VLSI cell in embedded applications, implementing an oscillation built-in self-test (OBIST) structure. The oscillation condition is achieved by means of a minimally intrusive switched feedback loop and the response evaluation circuit can be included in a very simple way, minimizing the hardware overhead. The fault simulation indicates a fault coverage of 100% for the circuit under test.Keywords: fault simulation, mixed signal testing, OBIST, oscillation-based test, VLSI testing.

Implementation of a Parallel Fault Simulation System using PODEM in a Hardware Accelerator using Python

VLSI Testing is one of the essential domains in recent times. With the channel length of the transistor decreasing continually, the number of transistors in a chip increases, thus increasing the probability of defects or faults. Automatic Test Pattern Generator is one way to find such input test vectors to the circuit, which will help identify the faults if present. PODEM algorithm is one such algorithm used in this regard. This paper helps in reducing the runtime of this algorithm by the parallelism approach. Different stuck-at faults in the gate level circuit are simulated parallelly.

AI-Powered Terahertz VLSI Testing Technology for Ensuring Hardware Security and Reliability

A low-power true single phase clock scan cell design for vlsi testing, ai powered thz vlsi testing technology, methods of automated test solutions design for vlsi testing, covert gates: protecting integrated circuits with undetectable camouflaging.

Integrated circuit (IC) camouflaging has emerged as a promising solution for protecting semiconductor intellectual property (IP) against reverse engineering. Existing methods of camouflaging are based on standard cells that can assume one of many Boolean functions, either through variation of transistor threshold voltage or contact configurations. Unfortunately, such methods lead to high area, delay and power overheads, and are vulnerable to invasive as well as non-invasive attacks based on Boolean satisfiability/VLSI testing. In this paper, we propose, fabricate, and demonstrate a new cell camouflaging strategy, termed as ‘covert gate’ that leverages doping and dummy contacts to create camouflaged cells that are indistinguishable from regular standard cells under modern imaging techniques. We perform a comprehensive security analysis of covert gate, and show that it achieves high resiliency against SAT and test-based attacks at very low overheads. We also derive models to characterize the covert cells, and develop measures to incorporate them into a gate-level design. Simulation results of overheads and attacks are presented on benchmark circuits.

A heuristic fault based optimization approach to reduce test vectors count in VLSI testing

A comprehensive review on applications of don’t care bit filling techniques for test power reduction in digital vlsi systems.

Massive power consumption during VLSI testing is a serious threat to reliability concerns of ubiquitous silicon industry. A significant amount of low-power methodologies are proposed in the relevant literature to address this issue of test mode power consumption and don’t care bit(X) filling approaches are one of them in this fraternity. These don’t care(X) bit filling techniques have drawn the significant attention of industry and academia for its higher compatibility with existing design flow as neither modification of the CUT is required nor they need to rerun the time-consuming ATPG process. This paper presents an empirical survey of those X-bit filling techniques, applied to mitigate prime two types of dynamic power dissipation namely shift power and capture power, occurred during full scan testing.

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VLSI 2020: IBM Research highlights nanosheet, AI processor and photonics advances

At the 2020 Symposia on VLSI Technology and Circuits this week, IBM Research is presenting a variety of papers, short courses, workshops and virtual sessions that demonstrate the latest advances in systems research. Our research spotlights key developments for hybrid cloud infrastructure and AI , marked by improvements in performance, energy efficiency, area scaling, and new workloads.

At VLSI’s first-ever virtual conference, IBM researchers are presenting their work on a universal air spacer compatible with different transistor architectures, whether it’s a fin field-effect transistor (FinFET) or a Nanosheet device architecture. Another team of IBM researchers demonstrates a new AI processor core design resulting in hardware utilization improvements that led to notable enhancements in training efficiency and performance. In a third paper, researchers focused on faster silicon photonics-based network switching, with one goal of eventually making these networks more useful for data centers.

The new air spacer design, taken by a transmission electron microscope.

In their paper, “Improved Air Spacer Co-Integrated with Self-Aligned Contact (SAC) and Contact Over Active Gate (COAG) for Highly Scaled CMOS Technology,” IBM researchers described how the new air spacer reduces effective capacitance – a critical factor impacting the characteristics of CMOS devices – by 15 percent through a reduction in the air spacer’s dielectric constant, leading to performance gains and power reductions at the same time. Although SAC and COAG have been adopted in FinFET technology to reduce the footprint of transistors and standard cells, co-integrating air spacers with SAC and COAG has been challenging.

The spacer is an isolation layer between a gate and the contacts for source and drain in the transistor – essentially, an electronic switch. When the gate is on, electricity flows from the source to the drain, and the gate serves as a valve. The spacer ensures the gate controls only the flow and that the gate and the source and drain are electrically isolated. Without the spacer, the gate cannot serve as a valve.

Researchers positioned their improved air spacer as a viable approach to enhance energy efficiency and performance of advanced CMOS technology by reducing parasitic capacitance, the unwanted capacitance between the parts of an electronic component or circuit due to their proximity to one another.

The paper introduces a new process to form air spacers and provides a practical approach to enabling an electronic device to consume less power while achieving better performance. Excitingly, introducing the new air spacer module into 7nm FinFET produces more performance gains than more costly and disruptive scaling of FinFET to 5nm. The researchers expect their work will help pave the way for their technology’s adoption in FinFET and NanoSheet transistors in the coming years.

Paper authors: Kangguo Cheng, Chanro Park, Heng Wu, Juntao Li, Son Nguyen, Jingyun Zhang, Miaomiao Wang, Sanjay Mehta, Zuoguang Liu,  Richard Conti, Nicolas Loubet, Julien Frougier, Andrew Greene, Tenko Yamashita, Bala Haran, Rama Divakaruni

AI Processor Core

The Digital AI Core with heterogeneous compute engines, featuring dual corelet architecture, shared L1 scratchpad, and memory neighbor interface.

A worldwide team of IBM researchers described a hardware demonstration of a processor core that can be applied to both AI training and inference applications in their paper, “A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.” The researchers achieved leading-edge compute efficiency for robust AI computations via efficient heterogeneous 2-D systolic array-SIMD (single instruction, multiple data) compute engines leveraging compact DLFloat16 Floating Point Units (FPUs). DLFloat is a 16-bit floating point format designed by IBM for deep learning training and inference.

For this study, the researchers optimized a Gen 1 core they first published in 2018, focusing on circuit design, architecture, and software enhancements to produce testchips with Gen 2 cores. This updated Gen 2 design features two corelets working in parallel and sharing memory to facilitate efficient computations. The resulting Gen 2 testchip achieved 5.5x power-efficiency improvements over their Gen 1 testchip for Deep Learning training and inference workflows while using a smaller supply voltage than their first-generation core. Each of the two corelets in the new design has 64 processing elements (each with multiple FPUs) that perform convolution and matrix multiplication operations, which is greater than 80 percent of overall workload in deep learning.

This advancement is part of the Digital AI Core accelerator research in the  IBM Research AI Hardware Center . AI hardware accelerators can be used for building and deploying neural network models  for applications such as speech recognition, natural language processing and computer vision. This latest chip focuses on 16-bit training and inference, but the researchers have also published progress towards   8 bit training  and  inference as low as 2 bits .

Paper authors: Jinwook Oh, SaeKyu Lee, Mingu Kang, Matthew Ziegler, Joel Silberman, Ankur Agrawal, Swagath Venkataramani, Bruce Fleischer, Michael Guillorn, Jungwook Choi, WeiWang, Silvia Mueller, Shimon Ben-Yehuda, James Bonanno, Nianzheng Cao, Robert Casatuta, Chia-Yu Chen, Matt Cohen, Ophir Erez, Thomas Fox, George Gristede, Howard Haynie, Vicktoria Ivanov, Siyu Koswatta, Shih-Hsien Lo, Martin Lutz, Gary Maier, Alex Mesh, Yevgeny Nustov, Scot Rider, Marcel Schaal, Michael Scheuermann, Xiao Sun, Naigang Wang, Fanchieh Yee, Ching Zhou, Vinay Shah, Brian Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang

Silicon Photonics

The silicon photonics switch module.

In the paper, “A Monolithically Integrated Silicon Photonics 8×8 Switch in 90nm SOI CMOS,” IBM researchers from the U.S. and Canada presented a silicon photonics-based network switch integrated with switching and control electronics. Silicon photonics, an evolving technology in which optical rays transfer data between computer chips, provides an affordable way to build faster switches. Optical rays can carry far more data in less time than electrical conductors.

IBM researchers have created one of the best performing high speed photonic switches, closing the performance gap with packet switching, which the internet uses to send data as well as information about where the data should be delivered. They have also simplified many problems that arise when trying to build electronics and photonics on the same chip. Their goal is to include all of the necessary electronics in order to reduce the packaging load and make a switch that’s both easier to manufacture and more affordable to implement.

The new optical-based circuit switching technology enables switch reconfiguration times of less than 15 nanoseconds while avoiding the high power of more conventional packet-based electronic switches, which require optical-to-electronic domain conversion. The technology uses a scalable process with simple flip chip packaging. Flip chip is a method for interconnecting integrated circuit chips, microelectromechanical systems, or other semiconductor components to external circuitry.

Paper authors: Jonathan E. Proesel, Nicolas Dupuis, Herschel Ainspan, Christian W. Baks, Fuad Doany, Nicolas Boyer, Elaine Cyr, Benjamin G. Lee

Additional Works

Other accepted VLSI papers from IBM and AI Hardware Center members, in addition to those above, include:

“Selective Enablement of Dual Dipoles for Near Bandedge Multi-Vt Solution in High Performance FinFET and Nanosheet Technologies,” R. Bao, K. Watanabe, J. Zhang, H. Zhou, M. Sankarapandian, J. Li, S. Pancharatnam, P. Jamison, R. G Southwick, M. Wang, J. J Demarest, J. Guo, N. Loubet, V. Basker, D. Guo, V. Narayanan, B. Haran, H. Bu, M. Khare

“Si Incorporation Into AsSeGe Chalcogenides for High Thermal Stability, High Endurance and Extremely Low Vth Drift 3D Stackable Cross-point Memory,” H. Y. Cheng, I. T. Kuo, W C. Chien, C. W. Yeh, Y. C. Chou, N. Gong, L. Gignac, C. H. Yang, C. W. Cheng, C. Lavoie, M. Hopstaken, B. R. Bruce, L. Buzi, E. K. Lai, F. Carta, A. Ray, M. H. Lee, H. Y.Ho, W. Kim, M. BrightSky, H. L. Lung

“Structural and Electrical Demonstration of SiGe Cladded Channel for PMOS Stacked Nanosheet Gate-All-Around Devices,” S.Mochizuki, B.Colombeau, J.Zhang, S. C.Kung, M.Stolfi, H. Zhou, M. Breton, K. Watanabe, J. Li, H. Jagannathan, M.Cogorno, T.Mandrekar, P.Chen, N. Loubet, S.Natarajan, B.Haran

“Composite Interconnects for High-Performance Computing Beyond the 7nm Node” P. Bhosale, S. Parikh, N. Lanzillo, T. Nogami, R. Tao, M. Gage, R. Shaviv, A. Simon, M. Stolfi, S. Reidy, N.Loubet, B. Haran

“A no-verification Multi-Level-Cell (MLC) operation in Cross-Point OTS-PCM” N. Gong, W. Chien, Y. Chou, C. Yeh, N. Li, H. Cheng, C. Cheng, I. Kuo, C. Yang, R. Bruce, A. Ray, L. Gignac, Y. Lin, C. Miller, T. Perri, W. Kim, L. Buzi, H. Utomo, F. Carta, E. Lai, H. Ho, H. Lung, M. BrightSky

“A 25-50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS” Y. You, G. Wiedemeier, C. Marquart, C. Steffen, E. English, De. Yilma, T. Pham, V. Nammi, J. Okyere, N. Blanchard, A. Sutton, Z. Zhang, D. Friend D. Barba, T. Bohlke, M. Spear, V. Raj, J. Crugnale, D. Dreps, P.A. Francese, M. Kossel, T. Morf

Additionally, at VLSI:

• Alberto Valdes-Garcia will give an invited talk on “Hardware-Software Co-Integration for Configurable 5G mmWave Systems” (Circuits JFS2.1 session)
• Mukta Farooq and Arvind Kumar will offer a short course on “ Heterogenous Integration Architectures for AI ”
• Nicholas Loubet will offer a short course on “ Nanosheet Transistor as a Replacement of FinFET for Future Nodes: Device Advantages & Specific Process Elements ”
• Mounir Meghelli will offer a short course on “ Advances and Trends in High-Speed Serial Links for High-Density IO Applications ”
• Robert Bruce will offer a workshop presentation on “ Designing Material Systems and Algorithms for Analog Computing ”

These advances are part of IBM’s systems research group, which includes initiatives focusing on hybrid cloud, AI hardware, and exploratory science.

• Kangguo Cheng

Advanced CMOS VLSI Technology for Low Power Analog System Design with High Gain

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April 26, 2024 report

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Research investigates radio emission of the rotating radio transient RRAT J1854+0306

by Tomasz Nowakowski , Phys.org

Using the Five-hundred-meter Aperture Spherical radio Telescope (FAST), Chinese astronomers have investigated radio emission from a rotating radio transient known as RRAT J1854+0306. Results of the study, published April 15 on the preprint server arXiv , shed more light on the properties of this transient.

Pulsars are highly magnetized, rotating neutron stars emitting a beam of electromagnetic radiation. They are usually detected in the form of short bursts of radio emission ; however, some of them are also observed via optical, X-ray and gamma-ray telescopes.

Rotating radio transients (RRATs) are a subclass of pulsars characterized by sporadic emission. The first objects of this type were identified in 2006 as sporadically appearing dispersed pulses, with frequencies varying from several minutes to several hours. However, the nature of these transients is still unclear. In general, it is assumed that they are ordinary pulsars that experience strong pulses.

So far, only slightly more than 100 RRATs have been found. Therefore, astronomers are interested in studying them in detail in order to improve our knowledge about their still largely unknown nature.

Discovered in 2009, RRAT J1854+0306 has a spin period of 4.56 seconds and dispersion measure of 192.4 pc/cm 3 . It exhibits occasional strong pulses and is among the strongest RRATs, which makes it possible to explore its emission details.

A team of astronomers led by Qi Guo of the Hebei Normal University in China conducted highly sensitive observations of RRAT J1854+0306 with the aim of investigating its polarized emission. For this purpose, they employed the central beam of FAST's 19-beam receiver with a frequency range of 1000 to 1500 MHz, which was divided into 2,048 channels.

The observations found that the emission from RRAT J1854+0306 is dominated by nulls with a nulling fraction of about 53.2%, which is interspaced by narrow (less than 1 degree) and weak (less than 0.5 mJy) pulses with occasional wide and intense bursts. It appears that individual pulses showcase diverse profile morphology, exhibiting single, double and multiple peaks.

According to the study, the pulses of RRAT J1854+0306 exhibit diverse polarization behaviors. Their degree of linear polarization can reach 100% for some pulses, and their circular polarization exhibits various senses and variation.

"These features are related to the density distribution of relativistic particles and their emission processes and/or caused by the propagation effects. For some pulses, the position angles depart a lot from the average one, which might be caused by emission generated from different plasma conditions of the magnetosphere," the authors of the paper explained.

All in all, based on the collected data, the researchers concluded that the behavior of polarized emission of RRAT J1854+0306 indicates that its emission originates from a magnetosphere similar to those of normal pulsars. This could have implications for the overall understanding of rotating radio transients, as the finding suggests that RRATs may have the same physical origins as normal pulsars.

Journal information: arXiv

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