- Search forums
Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
Welcome to EDAboard.com
Welcome to our site edaboard.com is an international electronics discussion forum focused on eda software, circuits, schematics, books, theory, papers, asic, pld, 8051, dsp, network, rf, analog design, pcb, service manuals... and a whole lot more to participate you need to register. registration is free. click here to register now..
- Digital Design and Embedded Programming
- PLD, SPLD, GAL, CPLD, FPGA Design
how to assign hex value to a variable
- Thread starter j hemangini
- Start date Aug 8, 2008
- Aug 8, 2008
j hemangini
Member level 1.
assign hex value I want to creat a code in which there is variabe name let Data_Byte and want assign hex value 0x41, initially to this variable. Binary equivalent of this value is 01000001. According to my requirement after every 100 clock cycle only one bit should be on out pin (from bit no 0 to 7 one by one after every 100 clock cycle). So the main thing i want to ask is that how can i define this variable and how one bit can be transferred from this value. thank you.
llopacinski2
Newbie level 2.
assign hex values in vhdl If I understood: vhdl: signal Data_Byte : std_logic_vector( 7 downto 0) := x"41"; fifth bit: one_bit <= Data_Byte(5); --(data conversion can be needed) verilog: reg [7:0] Data_Byte = 8'h41; fifth_bit = Data_Byte[ 5];
Member level 2
vhdl assign hex You have to use "signal" not "variable" in order to put it on FPGA pin. first declare it.. signal Data_Byte : std_logic_vector(7 downto 0); hex value assignment.. Data_Byte <= x"BC"; For your problem first initialize.. Data_Byte <= x"01"; then every 100th clock edge, left rotate (by one bit) the whole register content.
vhdl assign value thanks for your reply. now i understood how to define hex value. But what instruction should i write for shift right. Thank you.
assigning hex values to #define Shift operators: Let A = “10010101” A sll 2 = “01010100” --shift left logical, filled with ‘0’ A srl 3 = “00010010” --shift right logical, filled with ‘0’ A sla 3 = “10101111” --shift left arithmetic, filled with right bit A sra 2 = “11100101” --shift right arithmetic, filled with left bit A rol 3 = “10101100” --rotate left by 3 A ror 5 = “10101100” --rotate right by 5 where sll, srl, sla, sra, rol, ror are vhdl keywords. For your application, you have to use: "A rol 1"
shift left logical for hexadecimal your reply was very helpful for me. I m very greatful to u. thank you.
Similar threads
- Started by mahesh_namboodiri
- Jan 31, 2024
- Started by aminpix
- Jul 19, 2024
- Replies: 12
- Started by BALU@FPGA
- Jul 23, 2024
- Started by Ducatidragon916
- Jul 18, 2024
- Started by Sanila P
- May 14, 2024
Part and Inventory Search
Welcome to edaboard.com.
- This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register. By continuing to use this site, you are consenting to our use of cookies. Accept Learn more…
- Ask a Question
VHDL Hex Values?
How do I write hex numbers in VHDL?
Please log in or register to answer this question.
VHDL Hex Values
Quick syntax, please log in or register to add a comment..
© 2022 by Hardware Coder. User contributions are licensed under cc by-sa 4.0 with attribution required . Attribution means a link to the question, answer, user, etc on this site.
This site is owned and operated by Hardware Coder in McKinney, Texas.
Send Us A Message About Us
By using this site, you agree to the following:
Privacy Policy Terms and Conditions DMCA Policy Earnings Disclaimer Legal Disclaimer
How to assign a hex or decimal value to a std_logic_vector of length 19 bits?
A bird in the hand may be worth two in the bush, but it sure makes it hard to type.
-- Rob Gaddi, Highland Technology Email address is currently out of order
> I write almost exclusively Verilog code,
> I want to say: > > flash_addr_i <= 128; >
> > I can't believe there's no way to do this in VHDL? >
Kevin Jennings
Jonathan Bromley
>I write almost exclusively Verilog code, but I inherited a >VHDL project and I need to make some changes to it. >I'm trying to make this human-readable, but I'm not >versed with VHDL, so I have no clue even what to look this up >under: > >This code works, but it is not very readable: > >signal flash_addr_i : std_logic_vector (18 downto 0) ; >. . . > elsif ((flash_addr_i < 128) and write_flag = '1') then > -- How can a human being make sense of of this? > -- and why is 128 OK for the comparison above and not > -- for the assignment below?
> flash_addr_i <= "0000000000010000000"; > end if; >. . . >I want to say: > > flash_addr_i <= 128; > >But then I get messages about flash_addr_i is not compatible with >with type of 128.
>and if I try a hex constant like: > > flash_addr_i <= x"00080"; > >I get bit width mis-match problems.
>How can I write the equivalent of the Verilog: > >flash_addr_i <= 19'd128; >or >flash_addr_i <= 19'h80;
The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
> Assignment can be handled through > the TO_UNSIGNED function as: > > flash_addr_i <= TO_UNSIGNED(128, 19);
>> signal flash_addr_i : std_logic_vector (18 downto 0) ; >> . . .
So it seems fair to assume that the poor devil is saddled with old code that uses std_logic_unsigned instead of numeric_std. CONV_STD_LOGIC_VECTOR is what he needs.
[email protected]
The monitor is easily attached to an AHB interface.... http://bknpk.no-ip.biz/AHB_MON/ahb_mon_1.html
> I guess I'll use Jonathan's suggestion of adding 128
> to another constant vector. That works for XST, which > makes sense because everywhere in the code I see stuff > like: > > flash_addr_i <= flash_addr_i + 1; > > Adding an integer constant to a std_logic_vector.
> Unfortunately the project is also full of case statements > with binary strings for the case values, which makes it > hard to read, too. However I'll get to those when I find > out that they're broken...
> This should get me by until I convert the whole project > to Verilog. Usually that helps me to understand other > people's code anyway.
Not a good thing if the rest of your project team is using VHDL. Probably ought to invest in training instead. VHDL is quite simple once you get past the initial learning stuff.
> There is no project "team" at this company or in other words, > I am the team.
IMAGES
VIDEO