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vhdl illegal target for signal assignment

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Do you have any VHDL design you are proud of, or do you need help with some code this is the place for it.

Struggling with the implementation of the counter in VHDL, particularly with the error: Illegal target for signal assignment

So overall I'm trying to make a pattern recognizer that recognizes the pattern of 13 0's followed by 17 1's and so I am going to use two counters, one for the 0's and one for the 1's, however I keep getting errors from this one single line that seems to be messing it all up, here is the code for the first counter:

The line temp <= 0 gives the first error and I think the problem is trying to put an integer into a signal? But then I can't use a std_logic_vector throughout as typing out 32 bits each time is really tedious but I'm not really sure where I'm going wrong.

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Signal Assignment

 LRM §8.4, §9.5.

A signal assignment statement modifies the target signal

Description:

A Signal assignment statement can appear inside a process (sequential statement) or directly in an architecture (concurrent statement). The target signal can be either a name (simple, selected, indexed, or slice) or an aggregate .

A signal assignment with no delay (or zero delay) will cause an event after delta delay, which means that the event happens only when all of the currently active processes have finished executing (i.e. after one simulation cycle).

The default delay mode ( inertial ) means that pulses shorter than the delay (or the reject period if specified) are ignored. Transport means that the assignment acts as a pure delay line.

VHDL'93 defines the keyword unaffected which indicates a choice where the signal is not given a new assignment. This is roughly equivalent to the use of the null statement within case (see Examples).

  • Delays are usually ignored by synthesis tool.

Aggregate , Concurrent statement , Sequential statement , Signal , Variable assignment

Chapter 3 - Data Flow Descriptions

Section 6 - signal assignments.

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Illegal use of conditional assignment in process #151

@ozbenh

MayaPosch commented Feb 20, 2020

In multiple source files, a conditional signal assignment statement is used within a process, which is illegal in VHDL-2008. Instead an if statement or case statement should be used.

During compilation one will get errors such as:

This is in process 'wishbone_muxes' (line 31of wishbone_arbiter.vhdl:














Here both conditional assignments (lines 41 and 42) should be rewritten either as a case statement or if statement. The same error occurs in various other locations in other source files, which I can list here if needed.

@mikey

mikey commented Jun 11, 2020

which compiler are you using? We've been using GHDL and Vivado in VHDL-2008 mode and have not been hitting this.

We can fix them but without a way to test, we'll likely introduce similar issues in the future.

Sorry, something went wrong.

@ozbenh

ozbenh commented Jun 27, 2020

Right neither Vivado nor ghdl complains ... I'll fix it anyways

@mikey

eine commented Jul 2, 2020

Should lines 41 and 42 be the following:

wb_slave_in.ack when early_sel = i else '0'; wb_masters_out(i).stall <= wb_slave_in.stall when early_sel = i else '1';

I'd say that's precisely a feature which was NOT supported before VHDL 2008, but which is supported since then. Previously, it was only allowed outside of processes. Hence, I'd say the synthesizer/simulator used by was configured for VHDL <2008 (I assume, the default in the tool). Can you please confirm?

In this case, I would use a generate instead of a process, because it feels more natural from a hardware point of view (less softwareish). But I believe that's just a style preference.

ozbenh commented Jul 2, 2020

Allright, I'm confused :-) what you say the lines should be is exactly what they are today .. or am I missing something ?

Is that construct inside of a process supported or not in VHDL 2008 ? Since none of the tools we use complains I assume it is.

Out of curiosity, why do you prefer a generate statement in that case ?

eine commented Jul 2, 2020 • edited Loading

what you say the lines should be is exactly what they are today .. or am I missing something ?

Oh, I think this is because I'm not a native english speaker. Should I have used "Shall the OP mean the following with :"?

The lines are directly copied from 's comment above, and I believe that those are the same that you are using in the codebase today. The discussion is whether that's valid VHDL 2008 or not. It was said it is not. I argue that it is. Hence, I think that this issue is related to the OP's tool settings, and not something that needs to be fixed in microwatt.

It is. However, if you try to analyze it with GHDL or Vivado and VHDL 1993 or 2002, it should complain. That's precisely my point.

VHDL is a language which supports synthesizable and non-synthesizable features. When using non-synthesizable language features, it feels very much like Ada or C. Hence, it is common to use lots of processes and to describe many sequential snippets, as if we were writing "functions". In this context, advantages of VHDL as a modeling language rely on the strong typing and the inherent parallelism; which makes it much easier to describe concurrent threads and inter-process communication of otherwise sequential modules/functions/blocks. It is not a language for production code, because the runtime is slower than Ada or C. But I expect you understand the potential for "modelling" any kind of "complex highly concurrent system", including physical systems (absolutely unrelated to hardware or electronics).

However, when the synthesizable subset is used, VHDL is not a programming language anymore, but a description language for hardware (read RTL) designs. As a language that is describing hardware, everything is parallel/concurrent by nature. In any FPGA/ASIC, everything is running at the same time. In this context, sequential operations are awkward, very awkward, absolutely unnatural, something to run away from... There is hardly nothing sequential in RTL. All comes down to registers (FFs), logical gates (LUTs), muxes, DSPs, and few additional and ad-hoc hard-IP included in todays SoCs. All the sequences of events that need to be described in RTL can be done through FSMs, and a FSM is just a register and the "next state logic", which is combinatorial. So, I envision describing hardware in VHDL as being suprisingly similar to drawing the same design using Tikz (LaTeX) or any other similar tool for "drawing programmatically". I believe that a good hardware designer needs to foresee the RTL layout of the code that she/he is writing. The best way to do so is to take a library of synthesizable templates (such as the one provided by many vendor tools) and compose a structural description based on those. When you need to instantiate a component/entity multiple times, using a generate is the natural way to do it.

The point is that, in the end, all concurrent statements in VHDL have an equivalent implementation as a process. IIRC, that's actually how concurrent statements are defined in the standard. I believe it makes sense because tooling is written in software, so analyzers/simulators/synthesizers feel more comfortable with sequential definitions. That's why you can write VHDL using sequential statements only, ignoring the other sub-subset completely. Nevertheless, the fact that you can do it does not mean that you should do it.

Let's be specific:

(selected, candidate, busy, wb_slave_in, wb_masters_in) variable early_sel : wb_arb_master_t; begin early_sel := selected; if busy = '0' then early_sel := candidate; end if; wb_slave_out <= wb_masters_in(early_sel); for i in 0 to NUM_MASTERS-1 loop wb_masters_out(i).dat <= wb_slave_in.dat; wb_masters_out(i).ack <= wb_slave_in.ack when early_sel = i else '0'; wb_masters_out(i).stall <= wb_slave_in.stall when early_sel = i else '1'; end loop; end process;

There is no clock signal here. Hence, this is not a register nor any other construct which needs to take time into account. You are saying that , and (each of them) MUST be updated each time any of , , , OR are updated (because of the sensitivity list). Is that true (i.e. the hardware you want to describe)? Let's see:

candidate when busy = '0' else selected; wb_slave_out <= wb_masters_in(early_sel); gen: for i in 0 to NUM_MASTERS-1 generate wb_masters_out(i).dat <= wb_slave_in.dat; wb_masters_out(i).ack <= wb_slave_in.ack when early_sel = i else '0'; wb_masters_out(i).stall <= wb_slave_in.stall when early_sel = i else '1'; end generate;

It turns out that:

depends on and ONLY. And all we need to implement it in hardware is a 2-to-1 MUX. depends on and ONLY. And all we need to implement it is, also, an N-to-1 MUX, where N is the module of . depends on and ONLY. Regarding the implementation, there is a for , NUM_MASTERS 2-to-1 MUXes for each of and , and a decoder. Well, these last MUXes can be visualized as AND/OR gates with constant / , respectively.

It can be argued that the original process is almost as readable as this version, and I wouldn't complain about that, should it come from an experienced user. However, for unexperienced users, I believe the latter is significantly easier to understand. For example, should the design need to be pipelined by say registering signal :

(clk) begin if rising_edge(clk) then early_sel <= candidate when busy = '0' else selected; end if; end process; wb_slave_out <= wb_masters_in(early_sel); gen: for i in 0 to NUM_MASTERS-1 generate wb_masters_out(i).dat <= wb_slave_in.dat; wb_masters_out(i).ack <= wb_slave_in.ack when early_sel = i else '0'; wb_masters_out(i).stall <= wb_slave_in.stall when early_sel = i else '1'; end generate;

It's "natural" to visualize which parts are registered and which are not. If you try to make this change above, you'll find that it is not so evident.

Last, but not least, I don't know how will synthesis tools behave in this case. I think the code is simple enough for them to guess that does NOT depend on , , or and they should "optimize" non-needed "update triggers" (if this wording makes any sense at all...). However, strictly speaking, tools should not do that for you. You are describing something, and they should stick to it, even if it's wrong (i.e. it doesn't make sense). Hence, even if you use sequential statements, I would recommend to use three processes instead of a single one (you'll find that doing so is more verbose than using concurrent statements). Moreover, I invite you to try synthesizing all three versions and analyzing (visualizing) the output. Is exactly the same hardware?

Of course, I do understand that many of you are coming from a software engineering background and no one has explained this "formal" details of the language to you. Please do take the explanations above as strongly opinionated and VERY friendly. I don't mean to say you are doing it wrong, not at all. As long as the hardware you get generated is the one you mean to generate, it's ok. Just be aware that in hardware (as in software) "just compiling and running" does not mean it is ok. You need to read synthesis logs (or run lots of post-synthesis and post-implementation regression tests).

So I believe I understand what you mean. That said, it's my experience (but let me know if I'm wrong) that synthesizers generally ignore the sensitivity list of processes completely anyways. In fact in Microwatt we have bucketloads of processes without any. What we do try to do however is clearly separate synchronous processes (ie, registers) and combinational logic.

So in the specific case of the wishbone arbiter, early_sel is "early" specifically it's combinational. A separate process latches it. This allows us to update the muxes on the same cycle as the cyc is asserted and thus avoid a cycle latency when going from idle to having a master selected.

In the same file you can see wishbone_candidate is another combinational process with a "all" sensitivity list (because doing an accurate one here is tricky) which is effectively an encoder.

And finally I have a 3rd process that is synchronous which represent the register of the selected master.

This is based on a lot of VHDL code we've seen out there, and it's written with generating HW in mind. The one thing maybe
I could have done is move early_sel generation to its own process to separate it from the mux itself but if you look at the rest of microwatt which is using the "2 processes" vhdl technique, this is really minor compared to our gigantic combinational processes :)

Fundamentally, we rely on the fact that the synthesizer turns a process into a large logic equation, which I assume it normalizes and simplifies, in order to generate a corresponding combinatorial circuit.

I'm calling and here for advice. It is my understanding that, since was introduced in VHDL 2008, most synthesizers are expected to resolve the sensitivity list on their own. Maybe the need to be accurate when specifying the list of signals in the sensitivity list goes back to earlier versions of the standard (and the tools). However, I would expect a process with an empty sensitivity list to do effectively nothing at all. I.e., not to be "executed" even once, and removed from synthesis. I might be outdated here...

Yes, this is a perfectly valid approach. That's why I said that the preference to use concurrent statements only (mostly) is very opinionated.

it's combinational. A separate process latches it.

Since there is no "standard style guide" for VHDL, this is also acceptable.

The style you use (a single or multiple processes, or not using processes) should not have any impact on you being able to update the muxes on the same cycle as the is asserted. If tools are able to transform one representation into the other while preserving the same behaviour, humans can also do it. If there is some latency, it is because you are not doing it purely combinatorial. Which, BTW, you might want to do on purpose in other cases.

In the concurrent version above, all muxes are updated as soon as is updated. Well, there is a latency because of the routing and the gates, but it is immediate from a "synchronous logic" point of view.

I guess this is the point. From a hardware description perspective, the synthesizer does not need to normalize or simplify anything, unless told to do so. From a software perspective, the compiler is expected to provide the faster/smaller code that is behaviouraly correct, thus involving multiple opmitizations. So, the more sequential logic you use, the more you rely on the compiler doing the simplification. OTOH, when targeting FPGAs, the target is, in fact, a huge array of configurable/programmable bits. These details are probably more relevant when targeting ASICs.

1 make docker run --rm -v //t/microwatt://src:z -w //src ghdl/ghdl:buster-llvm-7 ghdl -c --std=08 -frelaxed -Psim-unisim -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o -Wl,sim_console_c.o -Wl,sim_jtag_socket_c.o decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl decode1.vhdl helpers.vhdl insn_helpers.vhdl gpr_hazard.vhdl cr_hazard.vhdl control.vhdl decode2.vhdl register_file.vhdl cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl logical.vhdl countzero.vhdl multiply.vhdl divider.vhdl execute1.vhdl loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl core.vhdl wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl spi_rxtx.vhdl spi_flash_ctrl.vhdl sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl sim_16550_uart.vhdl core_tb.vhdl -e core_tb error: cannot load package "vcomponents" ghdl: compilation error make: *** [Makefile:101: core_tb] Error 1

Hrm, can you open a separate issue for this ? it probably works without docker, not sure why. I build unisim/vcomponents as a library first then import it, maybe it doesn't find the unisim-obj08.cf that should get generated in sim-unisim/
  • 👍 1 reaction

@JimLewis

JimLewis commented Jul 2, 2020

Seems like there are two questions:

Hence, it is bad if a process does not have a sensitivity list or wait statement.
Without these a tool will warn, possible infinite loop. Sometimes I get these
warnings in testbenches test sequencers that call procedures which have
wait statements in them - generally I avoid the warning by adding a "wait ;"
as the last line of the process.

Continuing with 2:
A process without a sensitivity list immediately starts running
and does not suspend until it hits the first wait statement.

ozbenh commented Jul 2, 2020 • edited Loading

So a few things to clarify here.

Jim, you seem to confirm my earlier statement implicitly. A synthesizer ignores the sensitivity list (well, Vivado does warn if you get it wrong but that's about it). This isn't surprising, it uses the actual "code" to infer a logic equation and implements that. The sensitivity list is mostly useful for simulators.

Then when I say we don't always have a sensitivity list, what I mean here is that we often use "all". This is actually a sensitivity list, but in effect it means to run whenever any signal changes. It sounds wasteful, and maybe it is, but it wouldn't be particularly difficult for a simulator to build a more precise list on the first execution pass or at compile time and use that instead.

We use that a lot in Microwatt because Anton wanted to use the "2 process" VHDL coding technique which means you have a simple synchronous process to implement the pipeline register and a huge combinatorial one that is a function of that register and all inputs. And also I'm a tad lazy :)

That said, if ghdl doesn't do the above optimisation, then I suppose we might be able to speed things up by hand-crafting more precise sensitivity lists for various processes. I know I have myself been lax lately and tended to use either "all" for combinatorial processes or "clk" for synchronous ones.

Note: It surprises me that the concept of sensitivity list is still around. I might be missing something here but it sounds fairly trivial to me for anything that parses vhdl or verilog to infer a sensitivity list based on the signals used in the process (or always@ block).

I understand that in theory, one could purposefully write "code" that only interprets various signals when a specific signal changes, and this is in effect what we do in synchronous processes, however requiring an explicit list seems extremely error prone to me.

It would make sense to update the formal definition of HDLs such that sensitivity list become obsolete. They should be entirely derived from the actual code. Any input outside of a if *edge and any condition of such an if *edge.

A property of combinational logic is that it is sensitive to all signals that are read in the process. Hence, in RTL for combinational logic, "all" is the right answer.

Yes with flip-flops, only clock and any asynchronous control is required. Maybe a good optimizer would do as well with "all" if we are careful about how we code (which we must be for RTL).

WRT sensitivity lists, you are forgetting about behavioral code and testbenches where I want to run only if a specific signal changes.

WRT RTL coding guidelines, when they are too rigid I have seen them do bad things to code.

I tend to draw a block diagram of the code and then make the code a reflection of the block diagram. Today, since the tools are now generally good enough, the biggest thing we need to do is write code that is readable and maintainable - maybe with a few optimizations here and there. Generally this means I code a separate process for each separate item in the block diagram - perhaps grouping a couple of related things together.

To me readable RTL code means that a reviewer should be able to easily draw the block diagram of the code by reading the code - and quickly. If you can't do this then the coding guidelines need to be revised until you can.

A disciplined person can write readable code using only a single process. However, single process code leads people to temptation to mix things that break the spatial locality of code and make readability more challenging. Generally as the space increases between assignments to the same output, understanding decreases - of course there are exceptions, such as statemachines.

BTW, one of the thoughts about single process implementation is simulation optimization - which was done at a time when compilers were not as smart as they are now and computers were slow.

@eine

I'd like to stress again that you are doing it correctly. None of the style issues you mentioned is wrong per se. Moreover, using for combinatorial processes and only for synchronous ones (without any async reset) is the way to go since VHDL 2008 was published.

All the discussion above is about style preferences, readability and maintainability. GHDL today will accept and it should perform equally well with any of them.

I see it as roughly equivalent to event listeners when doing web frontend development in JavaScript (which is another highly concurrent ecosystem). You can register multiple listeners that will execute the same function, but not all the variables that are used in the functions need to trigger it. In VHDL, the sensitivity list is how you/we declare multiple event listeners at once.

I guess this is somehow conflicting with the message I tried to deliver before, because this is mostly useful for non-synthesizable code. For synthesis, and should be used almost exclusively.

, thanks a lot for your explanations. I must say I feel a little embarrassed with your last comment because you explained the point much shorter and clear than I did...

In fact, my first contact with GHDL 4 years ago was about being able to draw that block diagram automatically from the VHDL code. Not a "technology diagram", neither an "RTL diagram", but a "diagram of the code". Meaning that any entity should be a black box, each process should also be a black box, and concurrent statements in each architecture can be grouped in a single or multiple black boxes. See .

The TL;DR is that tools that do "elaboration for simulation" can provide a tree of the architecture, but cannot draw the lines between the blocks/modules/blackboxes. OTOH, "elaboration for synthesis" does have the information to draw the connections, but it does "too much" elaboration and some information about processes or how concurrent statements are described in the code might be lost.

The ecosystem changed quite a lot in the last 4 years. Back then GHDL didn't support synthesis and it was absolutely out of Tristan's scope. Now, ghdl + yosys allow to have "RTL diagrams" with open source tools (e.g. netlistsvg). Moreover is an unoptimized, unflattened VHDL 1993 netlist which tries to preserve naming of the original sources.

Hence, today, it might be possible to use/extend along with for not only adding FPGA/CPLD devices to the schematics, but for drawing the VHDL sources that correspond to those. I.e., the same schematic layout/manipulation engine might be used to design the board and the chip (down to RTL VHDL). Of course, this is just daydreaming because I don't have the knowledge to implement it myself. I keep trying periodically, tho.

See , which is a recent discussion focused on Verilog.

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@mikey

vhdl illegal target for signal assignment

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Signal Assignments in VHDL: with/select, when/else and case

Sometimes, there is more than one way to do something in VHDL. OK, most of the time , you can do things in many ways in VHDL. Let’s look at the situation where you want to assign different values to a signal, based on the value of another signal.

With / Select

The most specific way to do this is with as selected signal assignment. Based on several possible values of a , you assign a value to b . No redundancy in the code here. The official name for this VHDL with/select assignment is the selected signal assignment .

When / Else Assignment

The construct of a conditional signal assignment is a little more general. For each option, you have to give a condition. This means that you could write any boolean expression as a condition, which give you more freedom than equality checking. While this construct would give you more freedom, there is a bit more redundancy too. We had to write the equality check ( a = ) on every line. If you use a signal with a long name, this will make your code bulkier. Also, the separator that’s used in the selected signal assignment was a comma. In the conditional signal assignment, you need the else keyword. More code for the same functionality. Official name for this VHDL when/else assignment is the conditional signal assignment

Combinational Process with Case Statement

The most generally usable construct is a process. Inside this process, you can write a case statement, or a cascade of if statements. There is even more redundancy here. You the skeleton code for a process (begin, end) and the sensitivity list. That’s not a big effort, but while I was drafting this, I had put b in the sensitivity list instead of a . Easy to make a small misstake. You also need to specify what happens in the other cases. Of course, you could do the same thing with a bunch of IF-statements, either consecutive or nested, but a case statement looks so much nicer.

While this last code snippet is the largest and perhaps most error-prone, it is probably also the most common. It uses two familiar and often-used constructs: the process and the case statements.

Hard to remember

The problem with the selected and conditional signal assignments is that there is no logic in their syntax. The meaning is almost identical, but the syntax is just different enough to throw you off. I know many engineers who permanenty have a copy of the Doulos Golden Reference Guide to VHDL lying on their desks. Which is good for Doulos, because their name gets mentioned all the time. But most people just memorize one way of getting the job done and stick with it.

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generate signal assignment in vhdl

  • Thread starter ali.329
  • Start date Nov 4, 2016
  • Nov 4, 2016

Newbie level 2

" Illegal target for signal assignment." Click to expand...
"Unknown identifier A0_i." Click to expand...
Code VHDL - ]
fff is signal A0_0 : bit ; signal A0_1 : bit ; signal A0_2 : bit ; signal A0_3 : bit ;   begin       U0 : for i in 0 to 3 generate       U1 : A0_i <= a(i) and b(i) ;       end generate; end sss;

ThisIsNotSam

Advanced member level 5.

why wouldn't you make an array and use i to index? if you absolutely need all 4 A0 signals, you can make a temp array, work on it, and then feed the original signals.  

FvM

Super Moderator

Generate can access array elements but doesn't perform text manipulations of signal names. Need to define a bit_vector port signal.  

Thanks a lot. So there isn't any way to solve this problem with these signals name? I must define array.  

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ali.329 said: Thanks a lot. So there isn't any way to solve this problem with these signals name? I must define array. Click to expand...

Advanced Member level 4

You can do it with a 3rd party pre-processor that generates a new file from a template. At one point I had one that let me embed python code in a VHDL/Verilog file for the purpose of code generation.  

You can do it with a 3rd party pre-processor that generates a new file from a template. At one point I had one that let me embed python code in a VHDL/Verilog file for the purpose of code generation. Click to expand...

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VHDL signal assignment within a process not behaving correctly?

Here's the code I'm running

You would expect that res2 would always use the previous value of sig_s1 , but in simulation it's working with the updated ones, as if this was a sequential code. What gives?

Here's the waveform https://i.sstatic.net/GSXpc.jpg (res1 is the result if I used variable instead of the signal for sig_s1). I don't know how benchmarks work.

  • 1 show the full code with testbench please. if d1,d2 and d3 are all changing at the same time, then res2 should be using the old value. –  vipin Commented Nov 5, 2017 at 18:18
  • 5 Signal assignment is behaving correctly, but there's a mistaxe in the process sensitivity list. –  user1818839 Commented Nov 5, 2017 at 18:24
  • 1 Which signal in a right hand side of an assignment is not present in the process sensitivity list? –  user1155120 Commented Nov 5, 2017 at 18:45
  • 2 I looked at it. As Vipin says, show the full code and testbench too, not just a code snippet. –  user1818839 Commented Nov 5, 2017 at 19:45
  • 1 The edits don't help, especially since the signal names don't all match the waveform. What gives? You need to write a testbench and learn how to simulate properly, that's what gives. Once you can make this question an minimal reproducible example someone can help you, if you haven't figured it out in the process. –  user1818839 Commented Nov 6, 2017 at 7:58

What gives is that signals do not get updated until all the processes have suspended.

Suppose there is a change (an event ) on one or more of d1 , d2 or d3 . They are in the sensitivity list of the process, so the process starts executing.

1) First this line gets executed: sig_s1 <= d1 and d2; . This is a line with a signal assignment in it ( <= ). The effect of executing any line with a signal assignment in it is, if the value of that signal is to change, to schedule that change for sometime in the future. If no delay is specified (which is the case here), then that future time is the next iteration of the simulation, which will occur once all the processes have finished executing (have suspended).

2) Then this line gets executed res2 <= sig_s1 xor d3; . Since, the effect of executing the previous line was to schedule a change on sig_s1 for the future, the value of signal sig_s1 has yet to change when this line is executed . That is really, really important. Hence the bold type. Consequently, the previous value of signal sig_s1 will be used to evaluate the expression sig_s1 xor d3 . If this results in a change to signal res2 then that change will be scheduled for the next simulation iteration, too.

There are various solutions to your problem. The simplest is to add signal sig_s1 to the sensitivity list:

Then once any change on signal sig_s1 is actioned, the process is executed again (because signal sig_s1 is now in the sensitivity list. This line will be executed first sig_s1 <= d1 and d2 and, assuming signals d1 and d2 haven't already changed again, there will be no change to signal sig_s1 . Then the line res2 <= sig_s1 xor d3 will be executed immediately afterwards. Signal sig_s1 will now have its new value and so the value of signal res2 will be updated (on the next simulation iteration, as before).

However, I recommend you don't do that. You don't need a process at all with simple expressions like this. It would be much better to do away with the process and just use concurrent signal assignments , like this:

Each concurrent signal assignment (as the name suggests) runs concurrently and so is a process in itself. (So, now there are two concurrent processes). With a concurrent signal assignment, you get a sensitivity list for free. So, there is no possibility of missing a signal out of the sensitivity list. Not only that, it takes up less space on the page, which means that the reader can see more of the code at once and hence get a better understanding*.

Always implement simple combinational logic like this as concurrent signal assignments, not as a process.

*I'm a prolific commenter, which rather undoes that advantage. Ho hum.

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vhdl illegal target for signal assignment

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VHDL signal assignments

In architecture

so is this signal assignment in Architecture is correct or wrong

IS bit and std_logic having same condition and is it possible to assign the same to std_logic_vector as in assignment?

TonyM's user avatar

  • 1 \$\begingroup\$ 1. Please use the preview before posting, especially for code. 2. Does the value of the question increase for every question mark added? \$\endgroup\$ –  pipe Commented Feb 13, 2018 at 11:49
  • 2 \$\begingroup\$ This looks like homework so I'm not going to write an answer. It's incorrect, you need to convert at least one of the types. I have also edited the code to look nicer. In the future, remember to add four spaces on to the beginning of the parts that are code. \$\endgroup\$ –  stanri Commented Feb 13, 2018 at 11:56
  • \$\begingroup\$ Also have a look here: electronics.stackexchange.com/questions/51848/… \$\endgroup\$ –  Oldfart Commented Feb 13, 2018 at 11:57
  • \$\begingroup\$ @stanri, indentation advice is subjective but since we're here: I recommend to OP use 2 spaces, not 4. Avoids wasting line width. \$\endgroup\$ –  TonyM Commented Feb 13, 2018 at 12:21
  • 3 \$\begingroup\$ @TonyM the four spaces are defined by the markup. If you use two it doesn't put the code in a code block. See electronics.stackexchange.com/editing-help : "Indent four spaces to create an escaped <pre> <code> block" \$\endgroup\$ –  stanri Commented Feb 13, 2018 at 12:22

VHDL is a strongly typed language. All vectors which you concatanate on the right side should be of same data type. And the data type of the result of the right side expression should match with the data type of the left side expression. In VHDL, "bit" is a 2-valued data type and "std_logic" is an 8-valued data type. They both are different.

Mitu Raj's user avatar

  • 1 \$\begingroup\$ std_logic is a resolved std_ulogic which is a character enumerated type having 9 values ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-') count 'em. Enumerated means the values are named, character means at least some names are character literals. The value is positional (which doesn't correspond between the two types). Those 'vectors' are single dimensional array types with an element type that is a character enumerated type. The concatenation operator is predefined for all single dimensional array types. \$\endgroup\$ –  user8352 Commented Feb 13, 2018 at 19:35

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vhdl illegal target for signal assignment

IMAGES

  1. Solved Problem: (a) Write a VHDL signal assignment to

    vhdl illegal target for signal assignment

  2. PPT

    vhdl illegal target for signal assignment

  3. VHDL Signal Assignment and Resolved Signals Signal Assignment Statement

    vhdl illegal target for signal assignment

  4. PPT

    vhdl illegal target for signal assignment

  5. Concurrent Conditional and Selected Signal Assignment in VHDL

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  6. PPT

    vhdl illegal target for signal assignment

COMMENTS

  1. modelsim

    The idea here is to provide a name that can be indexed (8.4 Index names) for the generate statement assignment statement target. The issue is A0_i is an identifier (15.4) and indivisible lexical element (15.3). entity fff is. port (. a: in bit_vector(0 to 3); b: in bit_vector(0 to 3) ); end entity; architecture sss of fff is.

  2. [Moved] Illegal target for assignment

    Activity points. 299,653. VHDL doesn't know concatenations on the left-hand side of expression. Use an additional 64-bit wide signal or variable instead, assign respective parts of it to the port signals. In case of variable, assign under clock edge control, otherwise outside the process. Sep 8, 2014. #3. T.

  3. Struggling with the implementation of the counter in VHDL ...

    Struggling with the implementation of the counter in VHDL, particularly with the error: Illegal target for signal assignment . ... In VHDL, a register has as many bits as you define. So if you have a std_ulogic_vector(4 downto 0), you assign exactly five bits (or, to be precise, five std_logic entities) to it. Not more, not less.

  4. vhdl

    The Inside_process and Outside_process versions behave differently. If both designs work, it is mostly out of luck, because in this case Out_signal simply lags half a clock cycle when declared inside the process. Out_signal is assigned when the process triggers, which in this case occurs on rising and falling edges of clk.

  5. illegal reference of a signal during a static elaboration, vhdl

    ncvhdl_p: *E,ILSGRD (test.vhd,159|32): illegal reference of a signal (SIGNAL_ID) during static elaboration [12.3]. came from: IEEE Std 1076-1993, 12.3 Elaboration of a declarative part, para 3: In certain cases, the elaboration of a declarative item involves the evaluation of expressions that appear within the declarative item.

  6. vhdl

    1. Assignments in VHDL are neighter specified as registered or combinatorial. In VHDL the actual assignment type (the type of RTL logic generated) is just inferred. Registers in VHDL are created explicitly by assigning a signal on a clock edge, though just because a process has a clock it does not mean all signals in that block will be assigned ...

  7. Signal Assignment

    A Signal assignment statement can appear inside a process (sequential statement) or directly in an architecture (concurrent statement). The target signal can be either a name (simple, selected, indexed, or slice) or an aggregate. A signal assignment with no delay (or zero delay) will cause an event after delta delay, which means that the event ...

  8. VHDL Tutorial

    Section 6 - Signal Assignments. There are two forms of the signal assignment statement in addition to the simple signal assignments that have been used in the previous sections. These two forms are called the conditional signal assignment and the selected signal assignment statement. The following is an example of a conditional signal ...

  9. PDF 10 Concurrent Code

    VHDL. 10.2 whenThe Statement As seen in table 10.1, an assignment using the when statement is called a conditional assign-ment. Its syntax is presented below in two versions; note that the first ends with " else value," while the second ends with "when condition." target <= value when condition else value when condition else value;

  10. Illegal use of conditional assignment in process #151

    In multiple source files, a conditional signal assignment statement is used within a process, which is illegal in VHDL-2008. Instead an if statement or case statement should be used. During compilation one will get errors such as:

  11. Signal Assignments in VHDL: with/select, when/else and case

    With / Select. The most specific way to do this is with as selected signal assignment. Based on several possible values of a, you assign a value to b. No redundancy in the code here. The official name for this VHDL with/select assignment is the selected signal assignment. with a select b <= "1000" when "00", "0100" when "01", "0010" when "10 ...

  12. VHDL: Can a signal be used as an index for an aggregate?

    In software, or VHDL simulation, each variable assignment takes an execution cycle. In hardware, each variable assignment creates an logic node which can feed into other logic on the same variable, but it all happens during a single clock cycle. And later writing the variable with a constant can cause all the earlier circuitry to totally disappear.

  13. generate signal assignment in vhdl

    " Illegal target for signal assignment." Click to expand... and "Unknown identifier A0_i." Click to expand... also i don't permit to change signal name. ... VHDL is not a string manipulation language, and signal names are not strings that you can perform text manipulation on to construct new signal names. You can perhaps do this in some ...

  14. Solved VHDL Programming "illegal target for signal

    Answer to Solved VHDL Programming "illegal target for signal | Chegg.com

  15. Difference between Blocking and Non-Blocking assignment in VHDL

    Signal assignments don't happen immediately, but are scheduled to happen after the end of the current delta cycle, ... So perhaps this is a little like Verilog's non-blocking assignment. The delay in VHDL only applies to when the signal is scheduled relative to the current process time and never impacts the process time. Time in a process only ...

  16. VHDL illegal use of a signal declaraction

    That signal declaration can be made in the architecture declarative part (before the begin most immediately following the reserved word architecture in the architecture body). Making that change: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY work4 IS. PORT ( CS: IN STD_LOGIC; RD: IN STD_LOGIC; WR: IN STD_LOGIC;

  17. Why do we assign our outputs to signals first in VHDL?

    4. It's because you couldn't read from ports of type OUT in VHDL. If the value driving an OUT port was to be read within the design, a signal had to used to hold it, then that signal assigned to the OUT port. The capability to do so was added in VHDL-2008.

  18. VHDL signal assignment within a process not behaving correctly?

    architecture arch of func signal sig_s1: std_logic; begin sig_s1 <= d1 and d2; res2 <= sig_s1 xor d3; end arch; Each concurrent signal assignment (as the name suggests) runs concurrently and so is a process in itself. (So, now there are two concurrent processes). With a concurrent signal assignment, you get a sensitivity list for free.

  19. VHDL signal assignments

    1. VHDL is a strongly typed language. All vectors which you concatanate on the right side should be of same data type. And the data type of the result of the right side expression should match with the data type of the left side expression. In VHDL, "bit" is a 2-valued data type and "std_logic" is an 8-valued data type.