blocking assignment verilog

Verilog Blocking & Non-Blocking

Blocking assignment statements are assigned using = and are executed one after the other in a procedural block. However, this will not prevent execution of statments that run in a parallel block.

Note that there are two initial blocks which are executed in parallel when simulation starts. Statements are executed sequentially in each block and both blocks finish at time 0ns. To be more specific, variable a gets assigned first, followed by the display statement which is then followed by all other statements. This is visible in the output where variable b and c are 8'hxx in the first display statement. This is because variable b and c assignments have not been executed yet when the first $display is called.

In the next example, we'll add a few delays into the same set of statements to see how it behaves.

Non-blocking

Non-blocking assignment allows assignments to be scheduled without blocking the execution of following statements and is specified by a symbol. It's interesting to note that the same symbol is used as a relational operator in expressions, and as an assignment operator in the context of a non-blocking assignment. If we take the first example from above, replace all = symobls with a non-blocking assignment operator , we'll see some difference in the output.

See that all the $display statements printed 'h'x . The reason for this behavior lies in the way non-blocking assignments are executed. The RHS of every non-blocking statement of a particular time-step is captured, and moves onto the next statement. The captured RHS value is assigned to the LHS variable only at the end of the time-step.

So, if we break down the execution flow of the above example we'll get something like what's shown below.

Next, let's use the second example and replace all blocking statements into non-blocking.

Once again we can see that the output is different than what we got before.

If we break down the execution flow we'll get something like what's shown below.

Blocking vs. Nonblocking in Verilog

The concept of Blocking vs. Nonblocking signal assignments is a unique one to hardware description languages. The main reason to use either Blocking or Nonblocking assignments is to generate either combinational or sequential logic. In software, all assignments work one at a time. So for example in the C code below:

The second line is only allowed to be executed once the first line is complete. Although you probably didn’t know it, this is an example of a blocking assignment. One assignment blocks the next from executing until it is done. In a hardware description language such as Verilog there is logic that can execute concurrently or at the same time as opposed to one-line-at-a-time and there needs to be a way to tell which logic is which.

<=     Nonblocking Assignment

=      Blocking Assignment

The always block in the Verilog code above uses the Nonblocking Assignment, which means that it will take 3 clock cycles for the value 1 to propagate from r_Test_1 to r_Test_3. Now consider this code:

See the difference? In the always block above, the Blocking Assignment is used. In this example, the value 1 will immediately propagate to r_Test_3 . The Blocking assignment immediately takes the value in the right-hand-side and assigns it to the left hand side. Here’s a good rule of thumb for Verilog:

In Verilog, if you want to create sequential logic use a clocked always block with Nonblocking assignments. If you want to create combinational logic use an always block with Blocking assignments. Try not to mix the two in the same always block.

Nonblocking and Blocking Assignments can be mixed in the same always block. However you must be careful when doing this! It’s actually up to the synthesis tools to determine whether a blocking assignment within a clocked always block will infer a Flip-Flop or not. If it is possible that the signal will be read before being assigned, the tools will infer sequential logic. If not, then the tools will generate combinational logic. For this reason it’s best just to separate your combinational and sequential code as much as possible.

One last point: you should also understand the semantics of Verilog. When talking about Blocking and Nonblocking Assignments we are referring to Assignments that are exclusively used in Procedures (always, initial, task, function). You are only allowed to assign the reg data type in procedures. This is different from a Continuous Assignment . Continuous Assignments are everything that’s not a Procedure, and only allow for updating the wire data type.

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Procedural Assignments

Blocking assignments, race around condition: a problem with blocking assignment.

Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog

There are Two types of Procedural Assignments in Verilog.

• Blocking Assignments
• Nonblocking Assignments

To learn more about Delay: Read  Delay in Assignment (#) in Verilog

Blocking assignments

• Blocking assignments (=) are done sequentially in the order the statements are written.
• A second assignment is not started until the preceding one is complete. i.e, it blocks all the further execution before it itself gets executed.

Non-Blocking assignments

• Nonblocking assignments (<=), which follow each other in the code, are started in parallel.
• The right hand side of nonblocking assignments is evaluated starting from the completion of the last blocking assignment or if none, the start of the procedure.
• The transfer to the left hand side is made according to the delays. An intra- assignment delay in a non-blocking statement will not delay the start of any subsequent statement blocking or non-blocking. However normal delays are cumulative and will delay the output.
• Non-blocking schedules the value to be assigned to the variables but the assignment does not take place immediately. First the rest of the block is executed and the assignment is last operation that happens for that instant of time.

To learn more about Blocking and Non_Blocking Assignments: Read Synthesis and Functioning of Blocking and Non-Blocking Assignments

The following example shows  interactions  between blocking  and non-blocking for simulation only (not for synthesis).

For Synthesis (Points to Remember):

• One must not mix “<=” or “=” in the same procedure.
• “<=” best mimics what physical flip-flops do; use it for “always @ (posedge clk..) type procedures.
• “=” best corresponds to what c/c++ code would do; use it for combinational procedures.

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• Module Instantiation in Verilog

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Blocking and Non-blocking Assignment in Verilog

• Assignment is only done in procedural block(always ot initial block)
• Both combintational and sequential circuit can be described.
• Assignment can only possible to reg type irrespect of circuit type

Let's say we want to describe a 4-bit shift register in Verilog. For this, we are required to declare a 3-bit reg type variable.

The output of shift[0] is the input of shift[1], output of shift[1] is input of shift[2], and all have the same clock. Let's complete the description using both assignment operator.

Non-Blocking Assignment

When we do synthesis, it consider non-blocking assignment separately for generating a netlist. If we see register assignment in below Verilog code, all register are different if we consider non-blocking assignment separately. If you do the synthesis, it will generate 3 registers with three input/output interconnects with a positive edge clock interconnect for all register. Based on the Verilog description, all are connected sequentially because shift[0] is assigned d, shift[1] is assigned shift[0], and shift[2] is assigned shift[1].

Blocking Assignment

If we use blocking assignment and do the syhtheis, the synthesis tool first generate netlist for first blocking assignment and then go for the next blocking assignment. If in next blocking assignment, if previous output of the register is assigned to next, it will generate only a wire of previously assigned register.

In below Verilog code, even though all looks three different assignment but synthesis tool generate netlist for first blocking assigment which is one register, working on positive edge of clock, input d and output shift[0]. Since blocking assignment is used, for next blocking assignment, only wire is generated which is connected to shift[0]. Same is for next statement a wire is generated which is connected to shift[0].

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Comments (1)

hey in blocking assignment do we get shift in data i dont think so . we get all values same and equal to d.

Please do not focus on the module name; focus on how the netlist is generated after the synthesis.

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Difference between blocking and nonblocking assignment Verilog

I was reading this page http://www.asic-world.com/verilog/verilog_one_day3.html when I came across the following:

We normally have to reset flip-flops, thus every time the clock makes the transition from 0 to 1 (posedge), we check if reset is asserted (synchronous reset), then we go on with normal logic. If we look closely we see that in the case of combinational logic we had "=" for assignment, and for the sequential block we had the "<=" operator. Well, "=" is blocking assignment and "<=" is nonblocking assignment. "=" executes code sequentially inside a begin / end, whereas nonblocking "<=" executes in parallel.

I was fairly sure that nonblocking assignments were sequential while blocking assignments were parallel. After all, you can make blocking assignments with assign statements outside of always blocks, and those all run in parallel. Is this a mistake, or is the behavior different inside an always block? And, if the behavior IS different inside an always block, can nonblocking assignments be made outside an always block?

3 Answers 3

was fairly sure that nonblocking assignments were sequential while blocking assignments were parallel.

Blocking assignment executes "in series" because a blocking assignment blocks execution of the next statement until it completes. Therefore the results of the next statement may depend on the first one being completed.

Non-blocking assignment executes in parallel because it describes assignments that all occur at the same time. The result of a statement on the 2nd line will not depend on the results of the statement on the 1st line. Instead, the 2nd line will execute as if the 1st line had not happened yet.

• \$\begingroup\$ So what about assign statements? Are they just in a whole class of their own? \$\endgroup\$ –  Void Star Commented Nov 24, 2013 at 4:25
• 6 \$\begingroup\$ Yes, assign statements occur outside of always blocks and are generally used to describe to combinatorial (un-latched) logic (while always blocks, with some exceptions, describe sequential logic). AFAIK, assign statements always execute "in parallel" whenever their LHS has a value change. \$\endgroup\$ –  The Photon Commented Nov 24, 2013 at 4:28
• \$\begingroup\$ Okay... I'm starting to get the impression that Verilog just isn't the most elegantly designed language. This is gonna be like learning C was. \$\endgroup\$ –  Void Star Commented Nov 24, 2013 at 5:30
• 2 \$\begingroup\$ Verilog was designed to "describe" hardware that already exists. Using it as a language to design (synthesize) hardware is a hack. \$\endgroup\$ –  The Photon Commented Nov 24, 2013 at 6:02
• 6 \$\begingroup\$ if Verilog "like learning C" is a problem, take a look at VHDL. Some people have fairly strong preferences for one or the other. To some, VHDL is just too verbose. To me, it's much better thought out. (signal/variable assignment semantics are much clearer than blocking/non for example). stackoverflow.com/questions/13954193/… and sigasi.com/content/vhdls-crown-jewel You may prefer it or hate it. But it's worth a look. \$\endgroup\$ –  user16324 Commented Nov 24, 2013 at 10:20

Assign statements are neither "blocking" or "nonblocking", they are "continuous". The output of an assign statement is always equal to the specified function of it's inputs. "blocking" and "nonblocking" assignments only exist within always blocks.

A blocking assignment takes affect immediately it is processed. A nonblocking assignment takes place at the end of processing the current "time delta".

always blocks can be used to model either combinatorial or sequential logic (systemverilog has always_comb and always_ff to make this explicit). When modeling combinatorial logic it's usually more efficient to use = but it typically doesn't really matter.

When modelling sequential logic (e.g. always @(posedge clk) ) you normally use nonblocking assingments. This allows you to deterime the "state after the clock edge" in terms of "the state before the clock edge".

It is sometimes useful to use blocking assignments in sequential always blocks as "variables". If you do this then there are two key rules to bear in mind.

• Do not access a reg that is set with blocking assignments inside a sequential always block from outside the always block it is assigned in.
• Do not mix blocking and nonblocking assignments to the same reg.

Breaking these rules is likely to result in synthesis failures and/or behaviour differences between simulation and synthesis.

• \$\begingroup\$ ""Do not access a reg that is set with blocking assignments inside a sequential always block from outside the always block it is assigned in."" Can you please explain it? \$\endgroup\$ –  user125575 Commented Oct 4, 2016 at 6:44
• 2 \$\begingroup\$ Different sequential always blocks do not have a defined order. So reading a "reg" set with a blocking assingment in one always block from another always block will lead to unpredicable behaviour. \$\endgroup\$ –  Peter Green Commented Oct 4, 2016 at 15:23
• \$\begingroup\$ And even if it appears to work in simulation, a synthesis tool should look at that and say "nope". I use local regs for those intermediate vars, and make sure that they are always assigned to on every clock before being read, so that no 'storage' is implied. \$\endgroup\$ –  greggo Commented Mar 30, 2017 at 11:57
• \$\begingroup\$ IIRC at least in quartus it is only considered a warning not an error. \$\endgroup\$ –  Peter Green Commented Mar 30, 2017 at 11:59
• \$\begingroup\$ You should not be using nonblocking assignment in combinational logic, it can lock up the simulation. For more details, refer this answer: electronics.stackexchange.com/a/506047/238188 \$\endgroup\$ –  Shashank V M Commented Oct 5, 2020 at 14:55

The term Blocking assignment confuses people because the word blocking would seem to suggest time-sequential logic. But in synthesized logic it does not mean this , because everything operates in parallel .

Perhaps a less confusing term would be immediate assignment , which would still differentiate the intermediate results of combinational logic from the inputs to non-transparent memory elements (for example clocked registers), which can have delayed assignment .

From a legalistic standpoint, it all works out very nicely. You can, in fact, consider the = to be a blocking (time-sequential) operation even within always_comb sequences. However, the distinction between time-sequential and parallel makes absolutely no difference in this case because the always_comb block is defined to repeat until the instruction sequence converges on a stable state -- which is exactly what the hardware circuitry will do (if it meets the timing requirements).

The synthesizable subset of Verilog (and especially SystemVerilog) is extremely simple and easy to use -- once you know the necessary idioms. You just have to get past the clever use of terminology associated with the so-called behavioral elements in the language.

• \$\begingroup\$ In behavioral coding styles ( as compared to RTL ), the distinction between blocking and non-blocking can be relevant. In some cases, the synthesis tool may be able to infer functionally equivalent RTL from behavioral component designs. \$\endgroup\$ –  Brent Bradburn Commented Jul 21, 2015 at 17:28
• \$\begingroup\$ Of course the procedural mode of SystemVerilog, applicable especially to initial statements within program blocks, uses (time-sequential) blocking assignment exclusively. This is useful for testbench design, but generally not for RTL specification. \$\endgroup\$ –  Brent Bradburn Commented Dec 18, 2015 at 18:58

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Blocking Vs Non-blocking Assignments in Verilog

Welcome to our article on blocking and non-blocking assignments in Verilog. In hardware description language (HDL) coding, these assignments play a crucial role in defining the behavior of circuits. Understanding the differences and implications of blocking and non-blocking assignments is essential for creating efficient and reliable hardware designs.

In this article, we will explore the syntax, functionality, and impact of blocking and non-blocking assignments on circuit behavior. We will discuss their usage in Verilog and provide best practices for incorporating these assignments into your code.

Whether you’re new to Verilog or looking to enhance your knowledge, this article will serve as a comprehensive guide to understanding the intricacies of blocking and non-blocking assignments. Let’s dive in and explore the fascinating world of Verilog assignments together!

Table of Contents

What are Blocking Assignments?

In Verilog, blocking assignments are a fundamental concept used to assign values to variables within hardware description language (HDL) coding. These assignments follow a sequential execution model, where statements are executed one after another in the order they appear in the code.

The syntax for a blocking assignment involves using the assignment operator (=) to assign a value to a variable. For example:

Here, the value of variable “a” is assigned as 2, and the value of variable “b” is assigned as the result of “a + 3”.

Blocking assignments have an immediate impact on the simulation and time delays within a hardware design. When a blocking assignment is encountered in the code, the next statement is not executed until the assignment is complete. This means that any subsequent operations will be delayed until the assignment is finished.

To better understand the concept of blocking assignments, let’s consider a simple circuit design example.

Suppose we have a circuit that consists of two flip-flops connected in series. The output of the first flip-flop is connected to the input of the second flip-flop. By using blocking assignments, we can model the sequential behavior of the flip-flops.

Below is a diagram depicting the circuit:

To implement this circuit in Verilog, we can use blocking assignments to update the values of the flip-flop outputs based on the inputs and current state. Here’s an example:

In this example, the values of “Q1” and “Q2” are updated sequentially using blocking assignments within the “always” block. When the “reset” signal is asserted, both flip-flops are reset to 0. Otherwise, the value of “Q1” is updated with the value of the “data” input, and the value of “Q2” is updated with the current value of “Q1”.

By using blocking assignments, we can accurately model the behavior of the circuit and ensure that the values of the flip-flops are updated in the correct order. This sequential execution is essential for correctly simulating the behavior of hardware designs in Verilog.

In the next section, we will explore non-blocking assignments in Verilog and understand how they differ from blocking assignments.

What are Non-blocking Assignments?

Non-blocking assignments in Verilog are a powerful concept that allows for modeling concurrent behavior in hardware description language (HDL) designs. Unlike blocking assignments, which execute sequentially and can cause delays in simulation, non-blocking assignments enable parallel execution and facilitate efficient modeling of digital circuits.

Non-blocking assignments are denoted by the “ <=” operator ” in Verilog. They are used to update the values of registers and variables in a non-blocking fashion, meaning that the assignments occur concurrently without any temporal dependencies. This allows for efficient scheduling and evaluation of operations within a digital design.

One key advantage of non-blocking assignments is their ability to model clocked behavior and simulate flip-flops and sequential elements accurately. By using non-blocking assignments, the values of these elements are updated simultaneously, capturing the concurrent nature of digital systems.

Let’s take a look at an example to illustrate non-blocking assignments:

“`verilog always @(posedge clk) begin a In this code snippet, the non-blocking assignments “

” ensure that the values of variables

are updated concurrently on the positive edge of the clock signal. This behavior accurately models the flip-flop operation where the output values are synchronized with the clock cycles. As a result, non-blocking assignments provide a more realistic representation of digital circuits.

When using non-blocking assignments, it is crucial to understand the behavior of race conditions, where multiple assignments occur simultaneously. Proper coding techniques and design practices can help prevent race conditions and ensure accurate circuit modeling.

Key Features of Non-blocking Assignments:

• Update variables concurrently
• Model clocked behavior accurately
• Synchronize flip-flops with clock cycles
• Enable efficient scheduling and evaluation
• Prevent race conditions with coding techniques

Non-blocking assignments have revolutionized the way digital circuits are represented and simulated in Verilog. Their ability to model concurrent behavior and accurately capture clocked operations makes them an essential tool for HDL designers.

Now that we have explored non-blocking assignments, let’s move on to the next section where we will compare the differences between blocking and non-blocking assignments in Verilog.

Differences between Blocking and Non-blocking Assignments

In Verilog, blocking and non-blocking assignments are two fundamental concepts that play a crucial role in hardware description language (HDL) coding. Understanding the differences between these assignment types is essential to ensure accurate and efficient circuit design. In this section, we will explore the key distinctions between blocking and non-blocking assignments, focusing on their behavior during simulation, race conditions, and impact on timing and concurrency.

Behavior during Simulation

Blocking assignments in Verilog follow a sequential execution model, where each assignment is executed one after the other. This means that a blocked assignment must complete before the next assignment in the same procedural block can begin. Consequently, changes made to variables within a blocking assignment immediately affect subsequent assignments.

On the other hand, non-blocking assignments allow concurrent execution within the same procedural block. This concurrent execution model permits all non-blocking assignments in the block to execute simultaneously, regardless of their order. The values assigned to variables are stored and updated at the end of the procedural block, ensuring that changes made within the block take effect in the next simulation cycle.

Race Conditions

Race conditions can occur when multiple processes or procedural blocks attempt to access and modify the same variable simultaneously. Blocking assignments are more prone to race conditions as they evaluate and update variables immediately, potentially leading to unpredictable results when multiple processes access the same variables concurrently.

Non-blocking assignments, on the other hand, are specifically designed to handle concurrency and avoid race conditions. By storing and updating values at the end of the procedural block, non-blocking assignments ensure that each process accesses the most recent value without interfering with other processes or creating race conditions.

Impact on Timing and Concurrency

The choice between blocking and non-blocking assignments can significantly impact timing and concurrency in circuit design. Blocking assignments introduce a delay in the circuit because each assignment must complete before the next can begin. This delay can affect the overall timing of the circuit, potentially leading to unintended delays or timing violations.

Non-blocking assignments, on the other hand, allow for parallel execution, improving overall concurrency and performance. By eliminating the need for sequential execution, non-blocking assignments enhance the efficiency of the circuit, enabling faster and more accurate simulation results.

It’s worth noting that the behavior of blocking and non-blocking assignments can differ depending on the context and the specific Verilog simulator being used. It is essential to understand the nuances and limitations of each assignment type to ensure reliable and predictable hardware designs.

As illustrated in the table above, the differences between blocking and non-blocking assignments can be summarized as follows:

Best Practices for Using Blocking and Non-blocking Assignments in Verilog

When working with Verilog assignments, it is important to follow industry best practices to ensure efficient and reliable hardware description language (HDL) coding. Whether you are using blocking or non-blocking assignments, adhering to these guidelines can significantly improve the quality and functionality of your designs. In this section, we will discuss essential considerations and recommendations for using blocking and non-blocking assignments effectively in Verilog.

Coding Style

Consistency in coding style plays a crucial role in Verilog assignments. It is recommended to adopt a standardized coding style that is easily understandable and maintainable by the entire development team. Here are some best practices:

• Use meaningful variable and signal names to enhance readability and comprehension.
• Follow proper indentation and formatting conventions to improve code organization.
• Document your code using comments to provide context and explanations.
• Avoid the use of magical or hard-coded values; use constants or parameters instead.

An example of well-structured and readable Verilog code:

“` module example_module( input wire clk, input wire reset, output wire reg result );

reg [7:0] counter;

always @(posedge clk or posedge reset) begin if (reset) begin counter

Timing Constraints

When using blocking and non-blocking assignments, it is crucial to consider timing constraints to ensure accurate behavioral modeling of the hardware design. Here are some recommendations:

• Understand the underlying clock and event relationships and apply them appropriately.
• Avoid excessive blocking assignments in synchronous sequential logic to prevent timing issues.
• Use non-blocking assignments in sequential logic to model concurrent updates effectively.
• Ensure proper synchronization and sequencing in your designs to avoid race conditions.

Avoiding Common Pitfalls

When working with Verilog assignments, it is essential to be aware of common pitfalls that can introduce bugs or reduce the overall efficiency of your code. Here are some tips to avoid these pitfalls:

• Avoid mixing blocking and non-blocking assignments within the same always block to maintain code clarity and prevent unintended side effects.
• Do not use blocking assignments in combinational logic to prevent simulation mismatches.
• Be cautious while using non-blocking assignments in control logic, as they may cause unexpected behavior.
• Verify signal dependencies and ensure proper sequencing to prevent race conditions and simulation mismatches.
• Utilize simulation and linting tools to detect potential coding errors and improve code reliability.

By following these best practices, you can enhance the efficiency, reliability, and understandability of your Verilog designs. Adhering to standardized coding practices and paying attention to timing constraints will contribute to the overall success of your projects.

In conclusion, understanding the differences between blocking and non-blocking assignments in Verilog is crucial for efficient HDL coding. Throughout this article, we have explored the syntax, functionality, and implications of these assignments, shedding light on their impact on circuit behavior.

Blocking assignments in Verilog provide a straightforward approach to sequential execution, where each statement is executed one after another. On the other hand, non-blocking assignments allow for concurrent behavior, enabling the simulation of multiple processes that can execute in parallel.

By grasping the distinctions between these assignment types, designers can accurately model and simulate hardware designs, considering factors such as timing, synchronization, and race conditions. By adhering to best practices and guidelines, developers can optimize their Verilog code and avoid common pitfalls along the way.

To delve deeper into Verilog and master the art of HDL coding, we recommend further exploring comprehensive resources such as online tutorials, textbooks, and specialized forums. These platforms provide invaluable insights, examples, and discussions that can enhance your understanding of Verilog assignments and enable you to create efficient and reliable hardware designs.

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Verilog Blocking & Non-Blocking assignments elaborated

• Post author By Kevin
• Post date 20 October 2020

Blocking / Non-Blocking assignment rules

The main reason to use either Blocking or Non-Blocking assignments is to generate either combinational or sequential logic.

In non-blocking assignments (<=), all registers inside the always block are updated at the end. In blocking assignments (=), the registers are updated immediately.

Whether or not a flip-flop is inferred from a blocking assignment depends on whether or not the value of the variable being assigned needs to be remembered from one clock edge to the next.

It is good practice to separate combinational and sequential code as much as possible. In verilog, if we want to create sequential logic can use a clocked always block with non-blocking assignments. If on the other hand we want to create combinational logic can use an always block with blocking assignments. Best not to mix the two in the same always block but if they are mixed, need to be careful when doing this. Its up to the synthesis tools to determine whether a blocking assignment within a clocked always block will infer a flip-flop or not. If the signal is read before being assigned (eg fig2 below), the tools will infer sequential logic.

For simplicity purposes only showing in the verilog examples below the Always Block. These Always blocks are blocks of sequential logic since it involves a clock.

If on an active clock edge, the variable tmp is being assigned a value before it’s value is used (ie ‘write before read’ case) then no flip-flop is required & synthesis will not infer it as shown in fig1 below.

If the value of the reg is used before a new value is assigned to it (ie ‘read before write’ case), then the value that is used will be the value that was assigned on a previous clock. Therefore a flip-flop is required here as shown in fig2 below.

If all non-blocking assignments are used within the always block, it will look like :

Non-blocking assignments always imply flip-flops (order of assignments doesn’t matter). Same block diagram is inferred on both cases as shown in fig3 above. They result in simultaneous or parallel statement execution.

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Blocking assignments in always block verilog?

now I know in Verilog, to make a sequential logic you would almost always have use the non-blocking assignment (<=) in an always block. But does this rule also apply to internal variables? If blocking assignments were to be used for internal variables in an always block would it make it comb or seq logic?

So, for example, I'm trying to code a sequential prescaler module. It's output will only be a positive pulse of one clk period duration. It'll have a parameter value that will be the prescaler (how many clock cycles to divide the clk) and a counter variable to keep track of it.

I have count's assignments to be blocking assignments but the output, q to be non-blocking. For simulation purposes, the code works; the output of q is just the way I want it to be. If I change the assignments to be non-blocking, the output of q only works correctly for the 1st cycle of the parameter length, and then stays 0 forever for some reason (this might be because of the way its coded but, I can't seem to think of another way to code it). So is the way the code is right now behaving as a combinational or sequential logic? And, is this an acceptable thing to do in the industry? And is this synthesizable?

• 1 Does this answer your question? When does verilog use values from the current and when from the previous timeslot? –  dave_59 Commented Jul 16, 2020 at 6:29
• Synthesize it and see for yourself what it produces. Then ask yourself if that's what you want. –  TomServo Commented Jul 16, 2020 at 21:40

You should follow the industry practice which tells you to use non-blocking assignments for all outputs of the sequential logic. The only exclusion are temporary vars which are used to help in evaluation of complex expressions in sequential logic, provided that they are used only in a single block.

In you case using 'blocking' for the 'counter' will cause mismatch in synthesis behavior. Synthesis will create flops for both q and count . However, in your case with blocking assignment the count will be decremented immediately after it is being assigned the prescaled value, whether after synthesis, it will happen next cycle only.

So, you need a non-blocking. BTW initializing 'count' within declaration might work in fpga synthesis, but does not work in schematic synthesis, so it is better to initialize it differently. Unless I misinterpreted your intent, it should look like the following.

You do not need temp vars there, but you for the illustration it can be done as the following:

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